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| Preliminary *- SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SN8P1700A Series USER'S MANUAL Preliminary SN8P1702A SN8P1703A SONiX 8-Bit Micro-Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. SONiX TECHNOLOGY CO., LTD Page 1 Revision 0.5 Preliminary AMENDMENT HISTORY Version VER 0.1 VER 0.2 VER 0.3 Date Jul. 2003 Jul. 2003 Jul. 2003 Description V1.0 Preliminary Version Change watchdog overflow table 1. Modify selection table 2. DC current chars. Change 3. Feature change 4. Change SN8P1703 part number to SN8P1703A SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 5. Code option table has been relocated after pin description section. 6. Modify QTP approval sheet 7. Change Register description. 8. Add LVD typical value=1.8V in Elec. Char. Aug. 2003 VER 0.4 Sep. 2003 9. Add "Noise Filter" code option 1. Add SN8P1702A SSOP20 for Mask Mass production. 2. Add TC1 Timer in Update table. 3. Modify Chap. 8 table/figure no. 4. Modify TC0/TC1 timer description and table. 5. Modify PWM description and table. 6. Modify electrical characteristic table VER 0.5 Sep. 2003 1. Modify ADC convert time table 2. Modify the description of PEDGE register. 3. Modify the description of INTRQ register. 3. Remove approval sheet. 4. Separate the pin description section of SN8P1702A and SN8P1703A. 5. Remove PCB layout section 6. Add P-DIP 20 and Sop 20 package information. 7. Add SN8A1702B and SN8A1703A related description. SONiX TECHNOLOGY CO., LTD Page 2 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Table of Contents AMENDMENT HISTORY .............................................................................................................. 2 1 PRODUCT OVERVIEW ..................................................................................................... 8 GENERAL DESCRIPTION ........................................................................................................... 8 FEATURES SELECTION TABLE ................................................................................................. 8 MASK/OTP RELATIVE TABLE .......................................................................................................... 8 ADC GRADE TABLE .................................................................................................................... 8 UPGRADE FROM SN8P1702 (OLD VERSION OTP) ....................................................................... 9 SN8P1702A/SN8P1703A FEATURES ....................................................................................... 10 SYSTEM BLOCK DIAGRAM ...................................................................................................... 11 PIN ASSIGNMENT ..................................................................................................................... 12 SN8P1702A Pin Assignment................................................................................................... 12 SN8P1703A Pin Assignment................................................................................................... 14 PIN DESCRIPTIONS .................................................................................................................. 15 PIN CIRCUIT DIAGRAMS .......................................................................................................... 15 2 3 CODE OPTION TABLE ................................................................................................... 16 ADDRESS SPACES ........................................................................................................ 17 PROGRAM MEMORY (ROM)..................................................................................................... 17 OVERVIEW ............................................................................................................................. 17 USER RESET VECTOR ADDRESS (0000H) ......................................................................... 18 INTERRUPT VECTOR ADDRESS (0008H)............................................................................ 18 CHECKSUM CALCULATION.................................................................................................. 20 GENERAL PURPOSE PROGRAM MEMORY AREA ............................................................. 21 LOOKUP TABLE DESCRIPTION............................................................................................ 21 JUMP TABLE DESCRIPTION................................................................................................. 23 DATA MEMORY (RAM) .............................................................................................................. 25 SONiX TECHNOLOGY CO., LTD Page 3 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC OVERVIEW ............................................................................................................................. 25 WORKING REGISTERS............................................................................................................. 26 Y, Z REGISTERS .................................................................................................................... 26 R REGISTERS ........................................................................................................................ 27 PROGRAM FLAG ....................................................................................................................... 27 CARRY FLAG ......................................................................................................................... 27 DECIMAL CARRY FLAG......................................................................................................... 27 ZERO FLAG ............................................................................................................................ 27 ACCUMULATOR ........................................................................................................................ 28 STACK OPERATIONS................................................................................................................ 29 OVERVIEW ............................................................................................................................. 29 STACK REGISTERS............................................................................................................... 30 STACK OPERATION EXAMPLE ............................................................................................ 31 PROGRAM COUNTER............................................................................................................... 32 ONE ADDRESS SKIPPING .................................................................................................... 33 MULTI-ADDRESS JUMPING .................................................................................................. 34 4 5 6 ADDRESSING MODE...................................................................................................... 35 OVERVIEW................................................................................................................................. 35 IMMEDIATE ADDRESSING MODE ........................................................................................ 35 DIRECTLY ADDRESSING MODE .......................................................................................... 35 INDIRECTLY ADDRESSING MODE....................................................................................... 35 TO ACCESS DATA in RAM BANK 0....................................................................................... 36 SYSTEM REGISTER ....................................................................................................... 37 OVERVIEW................................................................................................................................. 37 SYSTEM REGISTER ARRANGEMENT (BANK 0) ..................................................................... 37 BYTES of SYSTEM REGISTER.............................................................................................. 37 BITS of SYSTEM REGISTER ................................................................................................. 38 POWER ON RESET ........................................................................................................ 39 SONiX TECHNOLOGY CO., LTD Page 4 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC OVERVIEW................................................................................................................................. 39 EXTERNAL RESET DESCRIPTION........................................................................................... 40 7 OSCILLATORS................................................................................................................ 42 OVERVIEW................................................................................................................................. 42 CLOCK BLOCK DIAGRAM ..................................................................................................... 42 OSCM REGISTER DESCRIPTION ......................................................................................... 43 EXTERNAL HIGH-SPEED OSCILLATOR............................................................................... 44 OSCILLATOR MODE CODE OPTION .................................................................................... 44 OSCILLATOR DEVIDE BY 2 CODE OPTION......................................................................... 44 OSCILLATOR SAFE GUARD CODE OPTION ....................................................................... 44 SYSTEM OSCILLATOR CIRCUITS ........................................................................................ 45 External RC Oscillator Frequency Measurement .................................................................... 46 INTERNAL LOW-SPEED OSCILLATOR .................................................................................... 47 SYSTEM MODE DESCRIPTION ................................................................................................ 48 OVERVIEW ............................................................................................................................. 48 NORMAL MODE ..................................................................................................................... 48 SLOW MODE .......................................................................................................................... 48 GREEN MODE........................................................................................................................ 48 POWER DOWN MODE........................................................................................................... 48 SYSTEM MODE CONTROL ....................................................................................................... 49 SYSTEM MODE BLOCK DIAGRAM ....................................................................................... 49 SYSTEM MODE SWITCHING ................................................................................................ 50 WAKEUP TIME........................................................................................................................... 51 OVERVIEW ............................................................................................................................. 51 HARDWARE WAKEUP ........................................................................................................... 51 EXTERNAL WAKEUP TRIGGER CONTROL ......................................................................... 52 8 TIMERS COUNTERS....................................................................................................... 53 WATCHDOG TIMER (WDT) ....................................................................................................... 53 T0M REGISTER............................................................................................................................. 54 TIMER COUNTER 0 (TC0) ......................................................................................................... 55 OVERVIEW ............................................................................................................................. 55 TC0M MODE REGISTER........................................................................................................ 56 SONiX TECHNOLOGY CO., LTD Page 5 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC0C COUNTING REGISTER................................................................................................ 57 TC0 Overflow Time ................................................................................................................. 57 TC0R AUTO-LOAD REGISTER.............................................................................................. 60 TC0 TIMER COUNTER OPERATION SEQUENCE................................................................ 61 TC0 CLOCK FREQUENCY OUTPUT (BUZZER) ................................................................... 63 TC0OUT FREQUENCY TABLE.................................................................................................. 64 TIMER COUNTER 1 (TC1) ......................................................................................................... 66 OVERVIEW ............................................................................................................................. 66 TC1M MODE REGISTER........................................................................................................ 67 TC1C COUNTING REGISTER................................................................................................ 68 TC1 Overflow Time ................................................................................................................. 68 TC1R AUTO-LOAD REGISTER.............................................................................................. 71 TC1 TIMER COUNTER OPERATION SEQUENCE................................................................ 72 TC1 CLOCK FREQUENCY OUTPUT (BUZZER) ................................................................... 74 PWM FUNCTION DESCRIPTION .............................................................................................. 75 OVERVIEW ............................................................................................................................. 75 PWM PROGRAM DESCRIPTION........................................................................................... 78 9 INTERRUPT..................................................................................................................... 79 OVERVIEW................................................................................................................................. 79 INTEN INTERRUPT ENABLE REGISTER ................................................................................. 80 INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 80 INTERRUPT OPERATION DESCRIPTION ................................................................................ 81 GIE GLOBAL INTERRUPT OPERATION ............................................................................... 81 INT0 (P0.0) INTERRUPT OPERATION .................................................................................. 82 TC0 INTERRUPT OPERATION .............................................................................................. 83 TC1 INTERRUPT OPERATION .............................................................................................. 84 MULTI-INTERRUPT OPERATION.......................................................................................... 85 10 I/O PORT............................................................................................................... 87 OVERVIEW................................................................................................................................. 87 I/O PORT FUNCTION TABLE .................................................................................................... 88 PULL-UP RESISTERS................................................................................................................ 89 I/O PORT DATA REGISTER ...................................................................................................... 92 SONiX TECHNOLOGY CO., LTD Page 6 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 11 12 13 14 15 4-CHANNEL ANALOG TO DIGITAL CONVERTER............................................. 94 OVERVIEW................................................................................................................................. 94 ADM REGISTER......................................................................................................................... 95 ADR REGISTERS....................................................................................................................... 95 ADB REGISTERS....................................................................................................................... 96 P4CON REGISTERS .................................................................................................................. 97 ADC CONVERTING TIME .......................................................................................................... 98 ADC CIRCUIT............................................................................................................................. 99 CODING ISSUE .................................................................................................. 100 TEMPLATE CODE.................................................................................................................... 100 PROGRAM CHECK LIST ......................................................................................................... 104 INSTRUCTION SET TABLE ............................................................................... 105 ELECTRICAL CHARACTERISTIC ..................................................................... 106 ABSOLUTE MAXIMUM RATING .............................................................................................. 106 STANDARD ELECTRICAL CHARACTERISTIC....................................................................... 106 PACKAGE INFORMATION ................................................................................ 107 P-DIP18 PIN ............................................................................................................................. 107 SOP18 PIN ............................................................................................................................... 108 P-DIP 20 PIN ............................................................................................................................ 109 SOP 20 PIN .............................................................................................................................. 110 SSOP20 PIN ............................................................................................................................. 111 SONiX TECHNOLOGY CO., LTD Page 7 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 1 PRODUCT OVERVIEW GENERAL DESCRIPTION The SN8P1702A/SN8P1703A is a series of 8-bit micro-controller. This chip is utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure. This chip is designed with the excellent IC structure including the large program memory OTP ROM, the massive data memory RAM, two 8-bit timer counters (TC0, TC1), a watchdog timer, three interrupt sources (TC0, TC1, INT0), an 4-channel ADC converter with 8-bit/12-bit resolution, two channels high speed PWM output (PWM0, PWM1), two channels buzzer output (BZ0, BZ1) and 8-level stack buffers. Besides, the user can choose desired oscillator configurations for the controller. There are four oscillator configurations to select for generating system clock, including High/Low Speed crystal, ceramic resonator or cost-saving RC. This series also includes an internal RC oscillator for slow mode controlled by programming. FEATURES SELECTION TABLE CHIP ROM RAM Stack Timer T0 TC0 TC1 SN8P1702A 1K*16 128 SN8P1703A 1K*16 128 8 V V V V 12 13 V 4ch 4ch I/O AVref ADC PWM Buzzer 2 2 Wakeup Pin no. 3 3 DIP18/SOP18/SSOP20 DIP20/SOP20/SSOP20 Package Table 1-1. Selection Table of SN8P1702A/SN8P1703A MASK/OTP Relative Table MASK Part Number Package Form SN8A1702A SN8A1702B SN8A1703A OTP Chip for Verification Assembler Declaration CHIP SN8P1702A CHIP SN8P1702AOTP CHIP SN8P1703A DIP18/SOP18 /SSOP20 SN8P1702A DIP18/SOP18 /SSOP20 SN8P1702A DIP20/SOP20 /SSOP20 SN8P1703A ADC GRADE TABLE CHIP SN8P1702A SN8P1703A SN8P1702A-12 SN8P1703A-12 PARAMETER Resolution No Mission Code Differential No linearity (DNL) Resolution No Mission Code Differential No linearity (DNL) Table 1-2. ADC Grade Table MIN 8 MAX 12 12 16 12 UNITS Bits Bits LSB Bits Bits LSB 10 12 4 SONiX TECHNOLOGY CO., LTD Page 8 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC UPGRADE FROM SN8P1702 (Old version OTP) Chip SN8P1702 SN8P1702A CHIP SN8P1702A < 1uA < 1mA < 3mA Yes Falling/Rising/Both Level change Only SSOP20 4 64 12 By Port @SET_PUR Yes High Clock SN8P1702A CHIP SN8P1702AOTP < 1uA < 1mA < 3mA Yes Falling/Rising/Both Level change Only SSOP20 4 Yes 128 12 Yes Yes By Pin PnUR Yes High Clock Internal RC SN8P1703A CHIP SN8P1703A < 1uA < 1mA < 3mA Yes Falling/Rising/Both Level change Yes 4 Yes 128 13 Yes Yes By Pin PnUR No High Clock Internal RC Assembly Declaration CHIP SN8P1702 Standby current (3V) 4MHz Operating (3V) 4MHz Operating (5V) Green Mode P0.0 Interrupt Edge P1 wake up AVREFH ADC Channel P4CON register RAM size GPIO TC1 Timer Fast PWM Pull-up Resistor Pull-up Register SN8P1702 Pin Compatible WDT clock source Internal RC always ON and WDT clock source fixed at internal RC 3uA 1.5mA 7mA Falling Low Level NO 4 64 12 By Port @SET_PUR Yes High Clock - - Yes Yes Power On Delay at 4MHz/3V MASK Type Package ~70ms SN8A1702A ~200ms SN8A1702A ~200ms SN8A1702B ~200ms SN8A1703A PDIP18/SOP18 PDIP18/SOP18/SSOP20 PDIP18/SOP18/SSOP20 PDIP20/SOP20/SSOP20 Notice: The SN8P1702 is not recommended for the new design. SONiX TECHNOLOGY CO., LTD Page 9 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SN8P1702A/SN8P1703A FEATURES Memory configuration OTP ROM size: 1K * 16 bits. RAM size: 128 * 8 bits. I/O pin configuration Input only: P0 Bi-directional: P1, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. Two 8-bit timer counters. (TC0, TC1). On chip watchdog timer. Eight levels stack buffer. Three interrupt sources Two internal interrupts: TC0, TC1 One external interrupts: INT0. An 4-channel 12-bit ADC Two channel high speed PWM output. Two channel Buzzer output. (BZ0/BZ1) Dual clock system offers four operating modes External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and internal low clock active Slow mode: Internal low clock only Green mode: Periodical wake-up by timer Sleep mode: Both high and internal low clock stop 59 powerful instructions Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Package (Chip form support) SN8P1702A -- PDIP 18 / SOP 18 / SSOP20 SN8P1703A-- PDIP 20 / SOP 20 / SSOP20 SONiX TECHNOLOGY CO., LTD Page 10 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SYSTEM BLOCK DIAGRAM PC IR FLA GS OTP ROM H-OSC Internal CLK Low Volt Detector Watch-Dog Timer TIMING GENERATOR PWM0 PWM0/Buzzer0 PWM1/Buzzer1 ALU PWM1 RAM AIN0~AIN3 ACC SYSTEM REGISTER ADC INTERRUPT CONTROL PORT 0 TIM ER & COUNTER PORT 1 PORT 4 PORT 5 Figure 1-1.Simplified System Block Diagram SONiX TECHNOLOGY CO., LTD Page 11 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC PIN ASSIGNMENT Format DescriptionG SN8P170XAY Y = P > PDIPA S > SOPA X> SSOP SN8P1702A Pin Assignment OTP Type: SN8P1702AS (SOP 18PIN) / SN8P1702AP (PDIP 18PIN) Pin compatible to the MASK version (SN8A1702AS/SN8A1702AP) P0.0/INT0 RST P1.1 P1.0 VSS P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SN8P1702AP SN8P1702AS VDD XIN XOUT P5.0 P5.1 P5.2 P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 VDD SN8P1702AX (SSOP 20PIN) Pin compatible to the MASK version (SN8A1702AX) VSS 1 U 20 VSS 2 19 P4.3/AIN2 3 18 P4.2/AIN1 4 17 P4.1/AIN1 5 16 P4.0/AIN0 6 15 AVREFH 7 14 VDD 8 13 P5.3/BZ1/PWM1 9 12 P5.2 10 11 SN8P1702AX P1.0 P1.1 RST P0.0/INT0 VDD XIN XOUT P5.0 P5.1 P5.4/BZ0/PWM0 OLD Version OTP Type: SN8P1702S (SOP 18PIN) / SN8P1702P (PDIP 18PIN) P0.0/INT0 RST P1.1 P1.0 VSS P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SN8P1702P SN8P1702S VDD/VPP XIN XOUT P5.0 P5.1 P5.2 P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 VDD Notice: The SN8P1702 is not recommended for the new design. SONiX TECHNOLOGY CO., LTD Page 12 Revision 0.5 Preliminary MASK Type: SN8A1702AS (SOP 18PIN) / SN8A1702AP (PDIP 18PIN) SN8A1702BS (SOP 18PIN) / SN8A1702BP (PDIP 18PIN) P0.0/INT0 RST P1.1 P1.0 VSS P4.3/AIN3 P4.2/AIN2 P4.1/AIN1 P4.0/AIN0 1 U 18 2 17 3 16 4 15 5 14 6 13 7 12 8 11 9 10 SN8A1702AP SN8A1702AS SN8A1702BP SN8A1702BS SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC VDD XIN XOUT P5.0 P5.1 P5.2 P5.3 P5.4/BZ0/PWM0 VDD SN8A1702AX (SSOP 20PIN) VSS 1 U 20 VSS 2 19 P4.3/AIN2 3 18 P4.2/AIN1 4 17 P4.1/AIN1 5 16 P4.0/AIN0 6 15 AVREFH 7 14 VDD 8 13 P5.3 9 12 P5.2 10 11 SN8A1702AX SN8A1702BX P1.0 P1.1 RST P0.0/INT0 VDD XIN XOUT P5.0 P5.1 P5.4/BZ0/PWM0 SONiX TECHNOLOGY CO., LTD Page 13 Revision 0.5 Preliminary SN8P1703A Pin Assignment OTP Type: SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SN8P1703AS (SOP 20PIN) / SN8P1703AP (PDIP 20PIN) / SN8P1703AX (SSOP 20PIN) P0.0/INT0 1 U 20 RST 2 19 P1.1 3 18 P1.0 4 17 VSS 5 16 P4.3/AIN3 6 15 P4.2/AIN2 7 14 P4.1/AIN1 8 13 P4.0/AIN0 9 12 AVREFH 10 11 SN8P1703AP SN8P1703AS SN8P1703AX VDD XIN XOUT P5.0 P5.1 P5.2 P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 P5.5 VDD MASK Type: SN8A1703AS (SOP 20PIN) / SN8A1703AP (PDIP 20PIN) / SN8A1703AX (SSOP 20PIN) P0.0/INT0 1 U 20 RST 2 19 P1.1 3 18 P1.0 4 17 VSS 5 16 P4.3/AIN3 6 15 P4.2/AIN2 7 14 P4.1/AIN1 8 13 P4.0/AIN0 9 12 AVREFH 10 11 SN8A1703AP SN8A1703AS SN8A1703AX VDD XIN XOUT P5.0 P5.1 P5.2 P5.3/BZ1/PWM1 P5.4/BZ0/PWM0 P5.5 VDD SONiX TECHNOLOGY CO., LTD Page 14 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC PIN DESCRIPTIONS PIN NAME VDD, VSS RST XIN, XOUT P0.0 / INT0 P1.0 ~ P1.1 P4.0 ~ P4.3 P5.0~P5.2, P5.5 P5.3 / BZ1 / PWM1 P5.4 / BZ0 / PWM0 AVREFH AIN0 ~ AIN3 TYPE P I I, O I I/O I/O I/O I/O I/O I I DESCRIPTION Power supply input pins for digital circuit. System reset input pin. Schmitt trigger structure, active "low", normal stay to "high". External oscillator pins. RC mode from XIN. Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resisters. Port 1.0~Port 1.1 bi-direction pins / Built-in pull-up resisters. Port 4.0~Port 4.3 bi-direction pins / Built-in pull-up resisters. Port 5.0~Port 5.2, P5.5 bi-direction pins / Built-in pull-up resisters. Port 5.3 bi-direction pin, TC1/2 signal output pin for buzzer or PWM1 output pin. Built-in pull-up resisters. Port 5.4 bi-direction pin, TC0/2 signal output pin for buzzer or PWM0 output pin. Built-in pull-up resisters. A/D converter high analog reference voltage. Analog signal input pins for ADC converter. Table 1-3. Pin Description PIN CIRCUIT DIAGRAMS Port1, 4, 5 structure Port0 structure PUR PUR PnM PnM Pin Pin Int. bus PnM Latch Int. bus Figure 1-2. Pin Circuit Diagram Note: All of the latch output circuits are push-pull structures. SONiX TECHNOLOGY CO., LTD Page 15 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 2 CODE OPTION TABLE Code Option Content RC 32K X'tal 12M X'tal 4M X'tal Enable Disable Enable Disable Enable Disable Enable Disable 8-bit 6-bit 5-bit 4-bit 8-bit 6-bit 5-bit 4-bit Enable Disable Enable Disable Always ON By_CPUM High_Clk High_Clk / 2 OSG Watch_Dog Security Function Description Low cost RC for external high clock oscillator Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator High speed crystal /resonator (e.g. 12M) for external high clock oscillator Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator External high clock divided by two, Fosc = high clock / 2 Fosc = high clock Enable Oscillator Safe Guard function Disable Oscillator Safe Guard function Enable Watch Dog function Disable Watch Dog function Enable ROM code Security function Disable ROM code Security function TC0 as 8-bit counter. TC0 as 6-bit counter. TC0 as 5-bit counter. TC0 as 4-bit counter. TC1 as 8-bit counter. TC1 as 6-bit counter. TC1 as 5-bit counter. TC1 as 4-bit counter. Enable Noise Filter function to enhance EMI performance Disable Noise Filter function Enable Low Power function to save Operating current Disable Low Power function Force Watch Dog Timer clock source come from INT 16K RC. Also INT 16K RC never stop both in power down and green mode that means Watch Dog Timer will always enable both in power down and green mode. Enable or Disable internal 16K(at 3V) RC clock by CPUM register TC0_Counter TC1_Counter Noise Filter Low Power INT_16K_RC Table 2-1. Code Option Table of SN8P1702A/SN8P1703A Notice: In high noisy environment, enable "Noise Filter", "OSG" and disable "Low Power" is strongly recommended. The side effect is to increase the lowest valid working voltage level if enable "Noise Filter" or "OSG" or "Low Power" code option. Enable "Low Power" option will reduce operating current except in 32K X'tal or slow mode. If users select "32K X'tal" in "High_Clk" option, assembler will force "OSG" to be enabled. If users select "RC" in "High_Clk" option, assembler will force "High_Clk / 2" to be enabled. SONiX TECHNOLOGY CO., LTD Page 16 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 3 ADDRESS SPACES PROGRAM MEMORY (ROM) OVERVIEW ROM Maps for SN8P1702A/SN8P1703A devices provide 1K x 16-bit program memory. The SN8P1702A/SN8P1703A program memory is able to fetch instructions through 12-bit wide PC (Program Counter) and can look up ROM data by using ROM code registers (R, X, Y, Z). In standard configuration, the device's 1,024 x 16-bit program memory has four areas: 1-word reset vector addresses 1-word Interrupt vector addresses 5-words reserved area 1K words (SN8P1702) All of the program memory is partitioned into three coding areas. The first area is located from 00H to 03H(The Reset vector area), the second area is a reserved area 04H ~07H, the third area is for the interrupt vector and the user code area from 0008H to 03FEH. The address 08H is the interrupt enter address point. ROM Reset vector General purpose area 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H . . 000FH 0010H 0011H . . 03FEH 03FFH User reset vector Jump to user start address Jump to user start address Jump to user start address Reserved Interrupt vector User interrupt vector User program General purpose area End of user program Reserved Figure 3-1. ROM Address Structure SONiX TECHNOLOGY CO., LTD Page 17 Revision 0.5 Preliminary USER RESET VECTOR ADDRESS (0000H) SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory. Example: After power on reset, external reset active or reset by watchdog timer overflow. CHIP SN8P1702A ORG JMP . ORG START: . . . . ENDP 0 START ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved 10H ; 0010H, The head of user program. ; User program ; End of program INTERRUPT VECTOR ADDRESS (0008H) A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory. Example 1: This demo program includes interrupt service routine and the user program is behind the interrupt service routine. CHIP SN8P1702A ORG JMP . ORG B0XCH B0MOV B0MOV . . . B0MOV B0MOV B0XCH RETI 0 START ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved ; Interrupt service routine ; B0XCH doesn't change C, Z flag ; Save PFLAG register in a buffer 8 A, ACCBUF A, PFLAG PFLAGBUF, A A, PFLAGBUF PFLAG, A A, ACCBUF ; Restore PFLAG register from buffer ; B0XCH doesn't change C, Z flag ; End of interrupt service routine START: . . . . JMP ENDP ; The head of user program. ; User program START ; End of user program ; End of program SONiX TECHNOLOGY CO., LTD Page 18 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Example 2: The demo program includes interrupt service routine and the address of interrupt service routine is in a special address of general-purpose area. CHIP SN8P1702A ORG JMP . ORG JMP ORG START: . . . . JMP MY_IRQ: B0XCH B0MOV B0MOV . . . B0MOV B0MOV B0XCH RETI ENDP A, ACCBUF A, PFLAG PFLAGBUF, A 0 START ; 0000H ; Jump to user program address. ; 0001H ~ 0007H are reserved 08 MY_IRQ 10H ; 0008H, Jump to interrupt service routine address ; 0010H, The head of user program. ; User program START ; End of user program ; The head of interrupt service routine ; B0XCH doesn't change C, Z flag ; Save PFLAG register in a buffer A, PFLAGBUF PFLAG, A A, ACCBUF ; Restore PFLAG register from buffer ; B0XCH doesn't change C, Z flag ; End of interrupt service routine ; End of program Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are as following. 1. The address 0000H is a "JMP" instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and necessary. 2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H (Example1) or to put a "JMP" instruction in 0008H then place the interrupt service routine in other general-purpose ROM area (Example2) to get more modularized coding style. SONiX TECHNOLOGY CO., LTD Page 19 Revision 0.5 Preliminary CHECKSUM CALCULATION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value. Example: The demo program shows user's code MOV B0MOV MOV B0MOV CLR CLR @@: CALL MOVC B0BSET ADD MOV ADC JMP AAA: INCMS JMP JMP END_CHECK: MOV CMPRS JMP MOV CMPRS JMP JMP YZ_CHECK: MOV CMPRS RET MOV CMPRS RET INCMS INCMS INCMS INCMS RET Y_ADD_1: INCMS NOP JMP CHECKSUM_END: .......... .......... END_USER_CODE: ;Label of program end Y @B ;increase Y ;jump to checksum calculate A,#04H A,Z A,#00H A,Y Z Z Z Z A,END_ADDR1 A,Z AAA A,END_ADDR2 A,Y AAA CHECKSUM_END ; Check if Z = low end address ; If Not jump to checksum calculate ; If Yes, check if Y = middle end address ; If Not jump to checksum calculate ; If Yes checksum calculated is done. ;check if YZ=0004H ;check if Z=04H ;if Not return to checksum calculate ;if Yes, check if Y=00H ;if Not return to checksum calculate ;if Yes, increase 4 to Z Z @B Y_ADD_1 ;Z=Z+1 ; If Z! = 00H calculate to next address ; If Z=00H increase Y YZ_CHECK FC DATA1,A A,R DATA2,A END_CHECK ; Call function of check yz value ; ; Clear C flag ; Add A to Data1 ; Add R to Data2 ; Check if the YZ address = the end of code how to avoid 0004H~0007H when calculated Checksum from 00H to the end of A,#END_USER_CODE$L END_ADDR1,A ; save low end address to end_addr1 A,#END_USER_CODE$M END_ADDR2,A ; Save middle end address to end_addr2 Y ; Set Y to 00H Z ; Set Z to 00H ;set YZ=0008H then return SONiX TECHNOLOGY CO., LTD Page 20 Revision 0.5 Preliminary GENERAL PURPOSE PROGRAM MEMORY AREA SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The 992-word at ROM locations 0010H~0FEFH are used as general-purpose memory. The area is stored instruction's op-code and look-up table data. The SN8P1702A/SN8P1703A includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, X, Y, Z). The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can't leap over the boundary by program counter automatically. Users need to modify the PCH value to "PCH+1" as the PCL overflow (from 0FFH to 000H). LOOKUP TABLE DESCRIPTION In the ROM's data lookup function, the X register is pointed to the highest 8-bit, Y register to the middle 8-bit and Z register to the lowest 8-bit data of ROM address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data stored in R register. Example: To look up the ROM data located "TABLE1". B0MOV B0MOV MOVC Y, #TABLE1$M Z, #TABLE1$L INCMS JMP INCMS NOP @@: TABLE1: MOVC . DW DW DW Z @F Y . 0035H 5105H 2012H ; To set lookup table1's middle address ; To set lookup table1's low address. ; To lookup data, R = 00H, ACC = 35H ; ; Increment the index address for next address ; Z+1 ; Not overflow ; Z overflow (FFH 00), Y=Y+1 ; Not overflow ; ; To lookup data, R = 51H, ACC = 05H. ; ; To define a word (16 bits) data. ;" ;" CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically. Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users can omit "B0MOV X, #TABLE1$H". SONiX ICE support more larger program memory addressing capability. So make sure X register is "0" to avoid unpredicted error in loop-up table operation. Example: INC_YZ Macro INC_YZ MACRO INCMS JMP INCMS NOP @@: ENDM Z @F Y ; Z+1 ; Not overflow ; Y+1 ; Not overflow SONiX TECHNOLOGY CO., LTD Page 21 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer following example for detailed information: Example: Increase Y and Z register by B0ADD/ADD instruction B0MOV B0MOV B0MOV B0ADD B0BTS1 JMP INCMS NOP GETDATA: MOVC Y, #TABLE1$M Z, #TABLE1$L A, BUF Z, A FC GETDATA Y ; To set lookup table's middle address. ; To set lookup table's low address ; Z = Z + BUF. ; Check the carry flag. ; FC = 0 ; FC = 1. Y+1. TABLE1: . DW DW DW . 0035H 5105H 2012H ; ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . ; ; To define a word (16 bits) data. ;" ;" SONiX TECHNOLOGY CO., LTD Page 22 Revision 0.5 Preliminary JUMP TABLE DESCRIPTION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way is easy to make a multi-stage program. When carry flag occurs after executing of "ADD PCL, A", it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words. Example : If PC = 0323H (PCH = 03HPCL = 23H) ORG B0ADD JMP JMP JMP JMP 0X0100 PCL, A A0POINT A1POINT A2POINT A3POINT ; The jump table is from the head of the ROM boundary ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H). Example: If "jump table" crosses over ROM boundary will cause errors. ROM Address . . . 0X00FD 0X00FE 0X00FF 0X0100 0X0101 . . . . . B0ADD JMP JMP JMP JMP . . PCL, A A0POINT A1POINT A2POINT A3POINT ; PCL = PCL + ACC, the PCH can't be changed. ; ACC = 0 ; ACC = 1 ; ACC = 2 jump table cross boundary here ; ACC = 3 SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro is maybe wasting some ROM size. Notice the maximum jump table number for this macro is limited fewer than 254. @JMP_A MACRO IF JMP ORG ENDIF ADD ENDM VAL (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) ($ | 0XFF) ($ | 0XFF) PCL, A Note: "VAL" is the number of the jump table listing number. SONiX TECHNOLOGY CO., LTD Page 23 Revision 0.5 Preliminary Example: "@JMP_A" application in SONIX macro file called "MACRO3.H". B0MOV @JMP_A JMP JMP JMP JMP JMP A, BUF0 5 A0POINT A1POINT A2POINT A3POINT A4POINT SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ; "BUF0" is from 0 to 4. ; The number of the jump table listing is five. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; ACC = 4, jump to A4POINT If the jump table position is from 00FDH to 0101H, the "@JMP_A" macro will make the jump table to start from 0100h. SONiX TECHNOLOGY CO., LTD Page 24 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC DATA MEMORY (RAM) OVERVIEW The SN8P1702A/SN8P1703A has internally built-in the data memory up to 256 bytes for storing the general-purpose data. 128 * 8-bit general purpose area in bank 0 128 * 8-bit system special register area The memory is separated into bank 0 and bank 1. The user can program RAM bank selection bits of RBANK register to access all data in any of the two RAM banks. The bank 0, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register. RAM location 000h " " " " " 07Fh 080h " " " " " 0FFh 000h~07Fh of Bank 0 = To store generalpurpose data (128 bytes). General purpose area BANK 0 080h~0FFh of Bank 0 = To store system registers (128 bytes). System register End of bank 0 area Figure 3-2. RAM Location Note: The undefined locations of system register area are logic "high" after executing read instruction "MOV A, M". SONiX TECHNOLOGY CO., LTD Page 25 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC WORKING REGISTERS The locations 82H to 84H of RAM bank 0 in data memory stores the specially defined registers such as register R, Z, Y, respectively shown in the following table. These registers can use as the general purpose of working buffer and be used to access ROM's and RAM's data. For instance, all of the ROM's table can be looked-up with R, Y and Z registers. The data of RAM memory can be indirectly accessed with Y and Z registers. 82H R R/W 83H Z R/W 84H Y R/W RAM Y, Z REGISTERS The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third, the registers can be address ROM location in order to look-up ROM data. Y initial value = 0000 0000 084H Y Bit 7 YBIT7 R/W Bit 6 YBIT6 R/W Bit 5 YBIT5 R/W Bit 4 YBIT4 R/W Bit 3 YBIT3 R/W Bit 2 YBIT2 R/W Bit 1 YBIT1 R/W Bit 0 YBIT0 R/W Z initial value = 0000 0000 083H Z Bit 7 ZBIT7 R/W Bit 6 ZBIT6 R/W Bit 5 ZBIT5 R/W Bit 4 ZBIT4 R/W Bit 3 ZBIT3 R/W Bit 2 ZBIT2 R/W Bit 1 ZBIT1 R/W Bit 0 ZBIT0 R/W The @YZ that is data point_1 index buffer located at address E7H in RAM bank 0. It employs Y and Z registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of Y register is pointed to RAM bank number and Z register is pointed to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly access mode. Example: If want to read a data from RAM address 25H of bank 1, it can use indirectly addressing mode to access data as following. B0MOV B0MOV B0MOV Y, #01H Z, #25H A, @YZ ; To set RAM bank 1 for Y register ; To set location 25H for Z register ; To read a data into ACC Example: Clear general-purpose data memory area of bank 1 using @YZ register. MOV B0MOV MOV B0MOV CLR_YZ_BUF: CLR DECMS JMP CLR END_CLR: @YZ Z CLR_YZ_BUF @YZ ; End of clear general purpose data memory area of bank 0 ; Clear @YZ to be zero ; Y - 1, if Y= 0, finish the routine ; Not zero A, #1 Y, A A, #07FH Z, A ; Y = 1, bank 1 ; Y = 7FH, the last address of the data memory area Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about Y, Z register look-up table application. SONiX TECHNOLOGY CO., LTD Page 26 Revision 0.5 Preliminary R REGISTERS SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC There are two major functions of the R register. First, R register can be used as working registers. Second, the R registers can be store high-byte data of look-up ROM data. After MOVC instruction executed, the high-byte data of a ROM address will be stored in R register and the low-byte data stored in ACC. R initial value = 0000 0000 082H R Bit 7 RBIT7 R/W Bit 6 RBIT6 R/W Bit 5 RBIT5 R/W Bit 4 RBIT4 R/W Bit 3 RBIT3 R/W Bit 2 RBIT2 R/W Bit 1 RBIT1 R/W Bit 0 RBIT0 R/W Note: Please consult the "LOOK-UP TABLE DESCRIPTION" about R register look-up table application. PROGRAM FLAG The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register. PFLAG initial value = xxxx x000 086H PFLAG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C R/W Bit 1 DC R/W Bit 0 Z R/W CARRY FLAG C = 1: If executed arithmetic addition with occurring carry signal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic "1". C = 0: If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with borrowing signal or executed rotation instruction with shifting out logic "0". DECIMAL CARRY FLAG DC = 1: If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction without borrow signal from high nibble. DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction with borrow signal from high nibble. ZERO FLAG Z = 1: After operation, the content of ACC is zero. Z = 0: After operation, the content of ACC is not zero. SONiX TECHNOLOGY CO., LTD Page 27 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ACCUMULATOR The ACC is an 8-bits data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can't be access by "B0MOV" instruction during the instant addressing mode. Example: Read and write ACC value. ; Read ACC data and store in BUF data memory MOV . BUF, A . ; Write a immediate data into ACC MOV . A, #0FH . ; Write ACC data from BUF data memory MOV . A, BUF . The system doesn't store ACC and PFLAG value as any interrupt service executed. ACC must be exchanged to another data memory defined by users. Thus, once interrupt occurs, these data must be stored in the data memory based on the user's program as follows. Example: ACC and working registers protection. ACCBUF INT_SERVICE: B0XCH B0XCH B0MOV B0MOV . B0MOV B0MOV B0XCH B0XCH RETI A, PFLAGBUF PFLAG,A A, ACCBUF A, ACCBUF ; Re-load PFLAG value ; Re-load ACC ; Re-load ACC ; Exit interrupt service vector A, ACCBUF A, ACCBUF A, PFLAG PFLAGBUF,A ; B0XCH doesn't change C, Z flag ; Store ACC value ; Store PFLAG value EQU 00H ; ACCBUF is ACC data buffer in bank 0. Notice: To save and re-load ACC data must be used "B0XCH" instruction, or the PLAGE value maybe modified by ACC. SONiX TECHNOLOGY CO., LTD Page 28 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC STACK OPERATIONS OVERVIEW The stack buffer of SN8P1702A/SN8P1703A has 8-level high area and each level is 12-bits length. This buffer is designed to save and restore program counter's (PC) data when interrupt service is executed. The STKP register is a pointer designed to point active level in order to save or restore data from stack buffer for kernel circuit. The STKnH and STKnL are the 12-bit stack buffers to store program counter (PC) data. STACK BUFFER PCH PCL RET / RETI CALL / interrupt STKP = 7 STKP = 6 STKP = 5 STKP = 4 STKP STK3H STK4H STK5H STK6H STK7H STK0H STK1H STK2H STKP STK3L STK4L STK5L STK6L STK7L STK0L STK1L STK2L STKP + 1 STKP - 1 STKP = 3 STKP = 2 STKP = 1 STKP = 0 Figure 3-3 Stack-Save and Stack-Restore Operation SONiX TECHNOLOGY CO., LTD Page 29 Revision 0.5 Preliminary STACK REGISTERS SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The stack pointer (STKP) is a 4-bit register to store the address used to access the stack buffer, 12-bits data memory (STKnH and STKnL) set aside for temporary storage of stack addresses. The two stack operations are writing to the top of the stack (Stack-Save) and reading (Stack-Restore) from the top of stack. Stack-Save operation decrements the STKP and the Stack-Restore operation increments one time. That makes the STKP always points to the top address of stack buffer and writes the last program counter value (PC) into the stack buffer. The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0. STKP (stack pointer) initial value = 0xxx 1111 0DFH STKP Bit 7 GIE R/W Bit 6 Bit 5 Bit 4 Bit 3 STKPB3 R/W Bit 2 STKPB2 R/W Bit 1 STKPB1 R/W Bit 0 STKPB0 R/W STKPBn: Stack pointer. (n = 0 ~ 3) GIE: Global interrupt control bit. 0 = disable, 1 = enable. More detail information is in interrupt chapter. Example: Stack pointer (STKP) reset routine. MOV B0MOV A, #00001111B STKP, A STKn (stack buffer) initial value = xxxx xxxx xxxx xxxx, STKn = STKnH + STKnL (n = 7 ~ 0) 0F0H~0FFH STKnH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SnPC9 R/W Bit 0 SnPC8 R/W 0F0H~0FFH STKnL Bit 7 SnPC7 R/W Bit 6 SnPC6 R/W Bit 5 SnPC5 R/W Bit 4 SnPC4 R/W Bit 3 SnPC3 R/W Bit 2 SnPC2 R/W Bit 1 SnPC1 R/W Bit 0 SnPC0 R/W STKnH: Store PCH data as interrupt or call executing. The n expressed 0 ~7. STKnL: Store PCL data as interrupt or call executing. The n expressed 0 ~7. SONiX TECHNOLOGY CO., LTD Page 30 Revision 0.5 Preliminary STACK OPERATION EXAMPLE SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The two kinds of Stack-Save operations to reference the stack pointer (STKP) and write the program counter contents (PC) into the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP is decremented and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as following table. Stack Level 0 1 2 3 4 5 6 7 >8 STKP Register STKPB2 STKPB1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 - STKPB3 1 1 1 1 1 1 1 1 - STKPB0 1 0 1 0 1 0 1 0 - Stack Buffer High Byte Low Byte STK0H STK1H STK2H STK3H STK4H STK5H STK6H STK7H STK0L STK1L STK2L STK3L STK4L STK5L STK6L STK7L - Description Stack Overflow Table 3-1. STKP, STKnH and STKnL relative of Stack-Save Operation The RETI instruction is for interrupt service routine. The RET instruction is for CALL instruction. When a Stack-Restore operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as following table. Stack Level 7 6 5 4 3 2 1 0 STKP Register STKPB2 STKPB1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 STKPB3 1 1 1 1 1 1 1 1 STKPB0 0 1 0 1 0 1 0 1 Stack Buffer High Byte Low Byte STK7H STK6H STK5H STK4H STK3H STK2H STK1H STK0H STK7L STK6L STK5L STK4L STK3L STK2L STK1L STK0L Description - Table 3-2. STKP, STKnH and STKnL relative of Stack-Restore Operation SONiX TECHNOLOGY CO., LTD Page 31 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC PROGRAM COUNTER The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 bits and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution. Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 11. PC Initial value = xxxx 0000 0000 0000 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 0 PCH Bit 8 0 Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 0 0 PCL Bit 2 0 Bit 1 0 Bit 0 0 PC PCH Initial value = xxxx 0000 0CFH PCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PC9 R/W Bit 0 PC8 R/W PCL Initial value = 0000 0000 0CEH PCL Bit 7 PC7 R/W Bit 6 PC6 R/W Bit 5 PC5 R/W Bit 4 PC4 R/W Bit 3 PC3 R/W Bit 2 PC2 R/W Bit 1 PC1 R/W Bit 0 PC0 R/W SONiX TECHNOLOGY CO., LTD Page 32 Revision 0.5 Preliminary ONE ADDRESS SKIPPING SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC There are 9 instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is matched, the PC will add 2 steps to skip next instruction. If the condition of bit test instruction is matched, the PC will add 2 steps to skip next instruction. B0BTS1 JMP . NOP B0MOV B0BTS0 JMP . NOP FC C0STEP ; Skip next instruction, if Carry flag = 1 ; Else jump to C0STEP. C0STEP: A, BUF0 FZ C1STEP ; Move BUF0 value to ACC. ; Skip next instruction, if Zero flag = 0. ; Else jump to C1STEP. C1STEP: If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction. CMPRS JMP . NOP A, #12H C0STEP ; Skip next instruction, if ACC = 12H. ; Else jump to C0STEP. C0STEP: If the result after increasing or decreasing by 1 is 0xFF or 0x00, the PC will add 2 steps to skip next instruction. INCS instruction: INCS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. C0STEP: INCMS instruction: INCMS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. C0STEP: DECS instruction: DECS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if ACC is not zero. C0STEP: DECMS instruction: DECMS JMP ... NOP BUF0 C0STEP ; Jump to C0STEP if BUF0 is not zero. C0STEP: SONiX TECHNOLOGY CO., LTD Page 33 Revision 0.5 Preliminary MULTI-ADDRESS JUMPING SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Users can jump round multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. If carry signal occurs after execution of ADD PCL, A, the carry signal will not affect PCH register. Example: If PC = 0323H (PCH = 03HPCL = 23H) ; PC = 0323H MOV B0MOV . . . MOV B0MOV A, #28H PCL, A . . . A, #00H PCL, A ; Jump to address 0328H ; PC = 0328H ; Jump to address 0300H Example: If PC = 0323H (PCH = 03HPCL = 23H) ; PC = 0323H B0ADD JMP JMP JMP JMP . PCL, A A0POINT A1POINT A2POINT A3POINT . ; PCL = PCL + ACC, the PCH cannot be changed. ; If ACC = 0, jump to A0POINT ; ACC = 1, jump to A1POINT ; ACC = 2, jump to A2POINT ; ACC = 3, jump to A3POINT ; SONiX TECHNOLOGY CO., LTD Page 34 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 4 ADDRESSING MODE OVERVIEW The SN8P1702A/SN8P1703A provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. The main purpose of the three different modes is described in the following: IMMEDIATE ADDRESSING MODE The immediate addressing mode uses an immediate data to set up the location (MOV A, #I, specific RAM. Immediate addressing mode MOV A, #12H ; To set an immediate data 12H into ACC B0MOV M,#I) in ACC or DIRECTLY ADDRESSING MODE The directly addressing mode uses address number to access memory location (MOV A,12H, MOV 12H,A). Directly addressing mode B0MOV A, 12H ; To get a content of location 12H of bank 0 and save in ACC INDIRECTLY ADDRESSING MODE The indirectly addressing mode is to set up an address in data pointer registers (Y/Z) and uses MOV instruction to read/write data between ACC and @YZ register (MOV A,@YZ, MOV @YZ,A). Example: Indirectly addressing mode with @YZ register CLR B0MOV B0MOV Y Z, #12H A, @YZ ; To clear Y register to access RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. SONiX TECHNOLOGY CO., LTD Page 35 Revision 0.5 Preliminary TO ACCESS DATA in RAM BANK 0 SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC In the RAM bank 0, this area memory can be read/written by these three access methods. Example 1: To use RAM bank0 dedicate instruction (Such as B0xxx instruction). B0MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC Example 3: To use indirectly addressing mode with @YZ register. CLR B0MOV B0MOV Y Z, #12H A, @YZ ; To clear Y register for accessing RAM bank 0. ; To set an immediate data 12H into Z register. ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC. SONiX TECHNOLOGY CO., LTD Page 36 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 5 SYSTEM REGISTER OVERVIEW The system special register is located at 80h~FFh. The main purpose of system registers is to control the peripheral hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, timers and counters by programming. The Memory map provides an easy and quick reference source for writing application program. To accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV, B0BSET, B0BCLR...). SYSTEM REGISTER ARRANGEMENT (BANK 0) BYTES of SYSTEM REGISTER SN8P1702 0 8 9 A B C D E F P1W P0 P0UR STK7 1 ADM P1M P1 P1UR STK7 2 R ADB STK6 3 Z ADR STK6 4 Y P4M P4 P4UR STK5 5 P5M P5 P5UR STK5 6 PFLAG STK4 7 @YZ STK4 8 T0M STK3 9 STK3 A OSCM TC0M STK2 B TC0C STK2 C TC1M STK1 D TC0R TC0C STK1 E P4CON PCL TC1R STK0 F PEDGE PCH STKP STK0 INTRQ INTEN Table 5-1. System Register Arrangement Description PFLAG = ADB = PnM = INTRQ = OSCM = TC0/1M = TC0/1C = TC0/1R = STKP = @HL = ROM page and special flag register. ADC's data buffer. Port n input/output mode register. Interrupts' request register. Oscillator mode register. Timer/Counter 0/1 mode register. Timer/Counter 0/1 counting register. Timer/Counter 0/1 auto-reload data buffer. Stack pointer buffer. RAM HL indirect addressing index pointer. R= Y, Z = RBANK = ADM = ADR = P1W = Pn = PnUR= INTEN = PCH, PCL = STK0~STK7 = @YZ = Working register and ROM lookup data buffer. Working, @YZ and ROM addressing register. RAM Bank Select register. ADC's mode register. ADC's resolution selects register. Port 1 wakeup register. Port n data buffer. Pull-up register Interrupts' enable register. Program counter. Stack 0 ~ stack 7 buffer. RAM YZ indirect addressing index pointer. Note: a). All of register names had been declared in SONiX 8-bit MCU assembler. b). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. c). It will get logic "H" data, when use instruction to check empty location. d). The low nibble of ADR register is read only. e). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. SONiX TECHNOLOGY CO., LTD Page 37 Revision 0.5 Preliminary BITS of SYSTEM REGISTER Address 082H 083H 084H 086H 0AEH 0B1H 0B2H 0B3H 0BFH 0C0H 0C1H 0C4H 0C5H 0C8H 0C9H 0CAH 0CDH 0CEH 0CFH 0D0H 0D1H 0D4H 0D5H Bit7 RBIT7 ZBIT7 YBIT7 ADENB ADB11 PEDGEN 0 0 0 0 0 0 WTCKS TC0R7 PC7 - SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 C DC Z P4CON3 P4CON2 P4CON1 P4CON0 ADS EOC GCHS CHS1 CHS0 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADCKS1 ADLEN ADB3 ADB2 ADB1 ADB0 P00G1 P00G0 0 0 0 0 0 P11W P10W 0 0 0 0 0 P11M P10M 0 0 0 P43M P42M P41M P40M 0 P55M P54M P53M P52M P51M P50M TC1IRQ TC0IRQ 0 0 0 0 P00IRQ TC1IEN TC0IEN 0 0 0 0 P00IEN WDRST WDRATE CPUM1 CPUM0 CLKMD STPHX 0 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC9 PC8 P00 P11 P10 P43 P42 P41 P40 P55 P54 P53 P52 P51 P50 R/W R/W R/W R/W R/W R/W R/W R R/W R/W W R/W R/W R/W R/W R/W R/W W R/W R/W R R/W R/W R/W 0D8H 0DAH 0DBH 0DCH 0DDH 0DEH 0DFH 0E0H 0E1H 0E4H 0E5H 0E7H 0F0H 0F1H 0F2H 0F3H " " " 0FCH 0FDH 0FEH 0FFH - - - - TC1X8 TC0X8 TC0GN - R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W " " " R/W R/W R/W R/W TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 TC1ENB TC1rate2 TC1rate1 TC1rate0 0 ALOAD1 TC1OUT PWM1OUT TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 GIE STKPB3 STKPB2 STKPB1 STKPB0 P00R P11R P10R P43R P42R P41R P40R P55R P54R P53R P52R P51R P50R @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 S7PC9 S7PC8 S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 S6PC9 S6PC8 " " " " " " " " " " " " " " " " " " " " " " " " S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 S1PC9 S1PC8 S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 S0PC9 S0PC8 Remarks R Z Y PFLAG P4CON ADM mode register ADB data buffer ADR register PEDGE P1W wakeup register P1M I/O direction P4M I/O direction P5M I/O direction INTRQ INTEN OSCM TC0R PCL PCH P0 data buffer P1 data buffer P4 data buffer P5 data buffer T0M TC0M TC0C TC1M TC1C TC1R STKP stack pointer P0UR P1UR P4UR P5UR @YZ index pointer STK7L STK7H STK6L STK6H " " " STK1L STK1H STK0L STK0H Table 5-2. Bit System Register Table Note: a). To avoid system error, please be sure to put all the "0" as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with "F" prefix code. d). "b0bset", "b0bclr", "bset", "bclr" instructions only support "R/W" registers. SONiX TECHNOLOGY CO., LTD Page 38 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 6 POWER ON RESET OVERVIEW This series provides two system resets. One is external reset and the other is low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value. The timing diagram is as following. VDD LVD Detect Level External Reset External Reset Detect Level LVD End of LVD Reset Internal Reset Signal End of External Reset Figure 6-1 Power on Reset Timing Diagram SONiX TECHNOLOGY CO., LTD Page 39 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC EXTERNAL RESET DESCRIPTION The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system operation. It is necessary that the VDD must be stable. VDD External Reset External Reset Detect Level Internal Reset Signal System Reset End of External Reset Figure 6-2 External Reset Timing Diagram Users must to be sure the VDD stable earlier than external reset (Figure 5-2) or the external reset will fail. The external reset circuit is a simple RC circuit as following. R 20K ohm VDD RST C 0.1uF VSS MCU VCC GND Figure 6-3. External Reset Circuit SONiX TECHNOLOGY CO., LTD Page 40 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC In worse power, condition as brown out reset. The reset pin may keep high level but the VDD is low voltage. That makes the system reset fail and chip error. To connect a diode from reset pin to VDD is a good solution. The circuit can force the capacitor to release electric charge and drop the voltage, and solve the error. DIODE R 20K ohm VDD RST C 0.1uF VSS MCU VCC GND Figure 6-4. External Reset Circuit with Diode SONiX TECHNOLOGY CO., LTD Page 41 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 7 OSCILLATORS OVERVIEW The SN8P1702A/SN8P1703A highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed clock frequency is supplied through on-chip RC oscillator circuit. The external high-speed clock and the internal low-speed clock can be system clock (Fosc). And the system clock is divided by 4 to be the instruction cycle (Fcpu). Fcpu = Fosc / 4 The system clock is required by the following peripheral modules: Timer counter 0 (TC0/TC1) Watchdog timer AD converter PWM output (PWM0/PWM1) Buzzer output (TC0OUT/TC1OUT) CLOCK BLOCK DIAGRAM HXRC(1:0) is code option *00= RC *01 =32 Khz Oscillator *10 = High Speed Oscillator (>10Mhz) *11 = Standard Oscillator (4Mhz) STPHX XIN XOUT CPUM0 LXOSC. CPUM0 fl HXRC OSG Divided by 2 1 : Disable 0 : Enable CLKMD fosc/4 CPUM0 HXOSC. fh Divided by 2 Divided by 4 fcpu OSG : Oscillator Safe Guard 1 : Disable -- System Default 0 : Enable Figure 7-1. Clock Block Diagram HXOSC: External high-speed clock. LXOSC: Internal low-speed clock. OSG: Oscillator safe guard. SONiX TECHNOLOGY CO., LTD Page 42 Revision 0.5 Preliminary OSCM REGISTER DESCRIPTION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock source and rate. OSCM initial value = 000x 000x 0CAH OSCM Bit 7 WTCKS R/W Bit 6 WDRST R/W Bit 5 Wdrate R/W Bit 4 CPUM1 R/W Bit 3 CPUM0 R/W Bit 2 CLKMD R/W Bit 1 STPHX R/W Bit 0 0 - Bit1 STPHX: External high-speed oscillator control bit. 0 = free run, 1 = stop. Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC oscillator is still running. CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. Bit2 Bit[4:3] CPUM[1:0]: CPU operating mode control bit. 00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved. Bit5 Wdrate: Watchdog timer rate select bit. 0 = Fcpu / 214 1 = Fcpu / 28 (The detail information is in watchdog timer chapter.) WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer's counter. (The detail information is in watchdog timer chapter.) WTCKS: Watchdog clock source select bit. 0 = Fcpu, 1 = internal RC low clock. Bit6 Bit7 SONiX TECHNOLOGY CO., LTD Page 43 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC EXTERNAL HIGH-SPEED OSCILLATOR This series can be operated in four different oscillator modes. There are external RC oscillator modes, high crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode (32K code option). For different application, the users can select one of satiable oscillator mode by programming code option to generate system high-speed clock source after reset. Example: Stop external high-speed oscillator. B0BSET FSTPHX ; To stop external high-speed oscillator only. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). OSCILLATOR MODE CODE OPTION This series has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main purpose is to support different oscillator types and frequencies. High-speed crystal needs more current but the low one doesn't. For crystals, there are three steps to select. If the oscillator is RC type, to select "RC" and the system will divide the frequency by 2 automatically. User can select oscillator mode from Code Option table before compiling. The table is as follow. Code Option 00 01 10 11 Oscillator Mode RC mode 32K 12M 4M Remark Output the Fcpu square wave from Xout pin. 32768Hz 12MHz ~ 16MHz 3.58MHz OSCILLATOR DEVIDE BY 2 CODE OPTION This series has an external clock divide by 2 function. It is a code option called "High_Clk / 2". If "High_Clk / 2" is enabled, the external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If "High_Clk / 2" is disabled, the external clock frequency is divided by 4 for the Fcpu. The Fcpu is equal to Fosc/4. Note: In RC mode, "High_Clk / 2" is always enabled. OSCILLATOR SAFE GUARD CODE OPTION This series builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and stops high frequency noise into system from external oscillator circuit. This function makes system to work better under AC noisy conditions. SONiX TECHNOLOGY CO., LTD Page 44 Revision 0.5 Preliminary SYSTEM OSCILLATOR CIRCUITS 20PF VDD XIN CRYSTAL 20PF XOUT VSS SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC MCU Figure 7-2. Crystal/Ceramic Oscillator R VDD XIN C XOUT VSS MCU Figure 7-3. RC Oscillator External Clock Input VDD XIN XOUT VSS MCU Figure 7-4. External clock input Note1: The VDD and VSS of external oscillator circuit must be from the micro-controller. Don't connect them from the neighbor power terminal. Note2: The external clock input mode can select RC type oscillator or crystal type oscillator of the code option and input the external clock into XIN pin. Note3: In RC type oscillator code option situation, the external clock's frequency is divided by 2. Note4: The power and ground of external oscillator circuit must be connected from the micro-controller's VDD and VSS. It is necessary to step up the performance of the whole system. SONiX TECHNOLOGY CO., LTD Page 45 Revision 0.5 Preliminary External RC Oscillator Frequency Measurement SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC There are two ways to get the Fosc frequency of external RC oscillator. One measures the XOUT output waveform. Under external RC oscillator mode, the XOUT outputs the square waveform whose frequency is Fcpu. The other measures the external RC frequency by instruction cycle (Fcpu). The external RC frequency is the Fcpu multiplied by 4. We can get the Fosc frequency of external RC from the Fcpu frequency. The sub-routine to get Fcpu frequency of external oscillator is as the following. Example: Fcpu instruction cycle of external oscillator B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. @@: B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. SONiX TECHNOLOGY CO., LTD Page 46 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC INTERNAL LOW-SPEED OSCILLATOR The internal low-speed oscillator is built in the micro-controller. The low-speed clock's source is a RC type oscillator circuit. The low-speed clock can supplies clock for system clock, timer counter, watchdog timer, SIO clock source and so on. Example: Stop internal low-speed oscillator. B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode). Note: The internal low-speed clock can't be turned off individually. It is controlled by CPUM0 bit of OSCM register. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relative between the RC frequency and voltage is as following. Internal RC vs. VDD 40 35 35.343 32.008 38.678 Fintrc (KHz) 30 25 22.003 25.338 28.673 20 15 11.998 15.333 18.668 10 7.329 8.663 5 0 1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50 VDD (Volts) Figure 7-5. Internal RC vs. VDD Diagram Example: To measure the internal RC frequency is by instruction cycle (Fcpu). The internal RC frequency is the Fcpu multiplied by 4. Therefore, we can get the Fosc frequency of internal RC from the Fcpu frequency. B0BSET B0BSET @@: B0BSET B0BCLR JMP P1.0 P1.0 @B ; Output Fcpu toggle signal in low-speed clock mode. ; Measure the Fcpu frequency by oscilloscope. P1M.0 FCLKMD ; Set P1.0 to be output mode for outputting Fcpu toggle signal. ; Switch the system clock to internal low-speed clock mode. SONiX TECHNOLOGY CO., LTD Page 47 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SYSTEM MODE DESCRIPTION OVERVIEW The chip is featured with low power consumption by switching around three different modes as following. High-speed mode Low-speed mode Power-down mode (Sleep mode) Green mode In actual application, the user can adjust the chip's controller to work in these three modes by using OSCM register. At the high-speed mode, the instruction cycle (Fcpu) is Fosc/4. At the low-speed mode and 3V, the Fcpu is 16KHz/4. NORMAL MODE In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is 3.58MHz/4 = 895KHz. All software and hardware are executed and working. In normal mode, system can get into power down mode and slow mode. SLOW MODE In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD = 1, the system switch to slow mode. In slow mode, the system works as normal mode but the slower clock. The system in slow mode can get into normal mode and power down mode. To set STPHX = 1 to stop the external high-speed oscillator, and then the system consumes less power. GREEN MODE The green mode is a less power consumption mode. Under green mode, there are only TC0 still counting and the other hardware stopping. The external high-speed oscillator or internal low-speed oscillator is operating. To set CPUM1 = 1 and CPUM0 = 0, the system gets into green mode. To set TC0GN = 1 (bit 1 of T0M) will enable TC0 green mode wakeup function. The system can be waked up to last system mode by TC0 timer timeout and P0 trigger signal. The green mode provides a time-variable wakeup function. Users can decide wakeup time by setting TC0 timer. There are two channels into green mode. One is normal mode and the other is slow mode. In normal mode, the TC0 timer overflow time is very short. In slow mode, the overflow time is longer. Users can select appropriate situation for their applications. Under green mode, the power consumption is 5u amp in 3V condition. POWER DOWN MODE The power down mode is also called sleep mode. The chip stops working as sleeping status. The power consumption is very less almost to zero. The power down mode is usually applied to low power consuming system as battery power productions. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal. SONiX TECHNOLOGY CO., LTD Page 48 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SYSTEM MODE CONTROL SYSTEM MODE BLOCK DIAGRAM Power Down Mode (Sleep Mode) P0, P1 wake-up function active. External reset circuit active. CPUM1, CPUM0 = 01 CLKMD = 1 Normal Mode CLKMD = 0 Slow Mode P0, P1 wake-up function active. TC0 time out. External reset circuit active. CPUM1, CPUM0 = 10 P0, P1 wake-up function active. TC0 time out. Green Mode External reset circuit active. Figure 7-6. System Mode Block Diagram Operating mode description MODE HX osc. LX osc. CPU instruction TC0 timer Watchdog timer Internal interrupt External interrupt Wakeup source NORMAL Running Running Executing *Active Active All active All active SLOW By STPHX Running Executing *Active Active All active All active GREEN By STPHX Running Stop *Active POWER DOWN (SLEEP) Stop Stop Stop Inactive REMARK * Active by program By INT_16K_RC By INT_16K_RC TC0 All active P0, P1, TC0 Reset All inactive All inactive P0, P1, Reset Table 7-1. Operating Mode Description SONiX TECHNOLOGY CO., LTD Page 49 Revision 0.5 Preliminary SYSTEM MODE SWITCHING Switch normal/slow mode to power down (sleep) mode. CPUM0 = 1 B0BSET FCPUM0 ; Set CPUM0 = 1. SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode. Switch normal mode to slow mode. B0BSET B0BSET FCLKMD FSTPHX ;To set CLKMD = 1, Change the system into slow mode ;To stop external high-speed oscillator for power saving. Note: To stop high-speed oscillator is not necessary and user can omit it. Switch slow mode to normal mode (The external high-speed oscillator is still running) B0BCLR FCLKMD ;To set CLKMD = 0 Switch slow mode to normal mode (The external high-speed oscillator stops) If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable. B0BCLR B0MOV DECMS JMP B0BCLR FSTPHX Z, #27 Z @B FCLKMD ; Turn on the external high-speed oscillator. ; If VDD = 5V, internal RC=32KHz (typical) will delay ; 0.125ms X 81 = 10.125ms for external clock stable ; ; Change the system back to the normal mode @@: Example: Go into Green mode and enable TC0 wakeup function. ; Set TC0 timer wakeup function. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BCLR B0BCLR B0BSET B0BSET ; Go into green mode B0BCLR B0BSET FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A FTC0IEN FTC0IRQ FTC0ENB FTC0GN FCPUM0 FCPUM1 ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = Fcpu / 64 ; To set TC0C initial value = 74H (To set TC0 interval = 10 ms) ; To disable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer ; To enable TC0 wakeup function ;To set CPUMx = 10 Note: If TC0ENB = 0 or TC0GN = 0, TC0 will not wakeup from green mode to normal/slow mode function. SONiX TECHNOLOGY CO., LTD Page 50 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC WAKEUP TIME OVERVIEW The external high-speed oscillator needs a delay time from stopping to operating. The delay is very necessary and makes the oscillator to work stably. Some conditions during system operating, the external high-speed oscillator often runs and stops. Under these conditions, the delay time for external high-speed oscillator restart is called wakeup time. There are two conditions need wakeup time. One is power down mode to normal mode. The other one is slow mode to normal mode. For the first case, SN8P1702A/SN8P1703A provides 2048 oscillator clocks to be the wakeup time. But in the last case, users need to make the wakeup time by themselves. HARDWARE WAKEUP When the system is in power down mode (sleep mode), the external high-speed oscillator stops. When waked up from power down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as the following. The Wakeup time = 1/Fosc * 2048 (sec) + X'tal settling time The x'tal settling time is depended on the x'tal type. Typically, it is about 2~4mS. Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the wakeup time, the system goes into normal mode. The wakeup time of P0, P1 wakeup function is as the following. The wakeup time = 1/Fosc * 2048 = 0.57 ms (Fosc = 3.58MHz) The total wakeup time = 0.57ms + x'tal settling time Under power down mode (sleep mode), there are only I/O ports with wakeup function wake the system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but the Port 1 is controlled by the P1W register. P1W initial value = xxxx xx00 0C0H P1W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 P11W W Bit 0 P10W W Bit[1:0] P11W,P10W:Port 1 wakeup function control bits. 0 = Disable each pin of Port1 wakeup function, 1 = Enable each pin of Port 1 wakeup function SONiX TECHNOLOGY CO., LTD Page 51 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC EXTERNAL WAKEUP TRIGGER CONTROL In the SN8P1702A/SN8P1703A, the wakeup trigger direction is control by PEDGE register. PEDGE initial value = 0xx0 0xxx 0BFH PEDGE Bit 7 PEDGEN R/W Bit 6 Bit 5 Bit 4 P00G1 R/W Bit 3 P00G0 R/W Bit 2 Bit 1 Bit 0 - Bit7 PEDGEN: Interrupt and wakeup trigger edge control bit. 0 = Disable edge trigger function. Port 0: Low-level wakeup trigger and falling edge interrupt trigger. Port 1: Low-level wakeup trigger. 1 = Enable edge trigger function. P0.0: Wakeup and interrupt trigger is controlled by P00G1 and P00G0 bits. Port 1: Level change (falling or rising edge) wakeup trigger. P00G[1:0]: Port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. Bit[4:3] SONiX TECHNOLOGY CO., LTD Page 52 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 8 TIMERS COUNTERS WATCHDOG TIMER (WDT) The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program gets in the unknown status by noise interference, The WDT's overflow signal will reset this chip and restart operation. The instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program within a given period. If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate different output timings, the user can control watchdog timer by modifying the Wdrate control bits of OSCM register. The watchdog timer will be disabled at green and power down modes. OSCM initial value = 0000 000x 0CAH OSCM Bit 7 WTCKS R/W Bit 6 WDRST R/W Bit 5 Wdrate R/W Bit 4 CPUM1 R/W Bit 3 CPUM0 R/W Bit 2 CLKMD R/W Bit 1 STPHX R/W Bit 0 - Bit1 STPHX: External high-speed oscillator control bit. 0 = free run, 1 = stop. Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC oscillator is still running. CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. Bit2 Bit[4:3] CPUM[1:0]: CPU operating mode control bit. 00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved. Bit5 Wdrate: Watchdog timer rate select bit. 0 = Fcpu / 214 1 = Fcpu / 28 WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer's counter. (The detail information is in watchdog timer chapter.) WTCKS: Watchdog clock source select bit. 0 = Fcpu, 1 = internal RC low clock. WTCKS 0 0 0 0 1 WTRATE 0 1 0 1 CLKMD 0 0 1 1 Watchdog Timer Overflow Time 1 / ( Fcpu / 214 / 16 ) = 293 ms, Fosc=3.58MHz 1 / ( Fcpu / 28 / 16 ) = 500 ms, Fosc=32768Hz 1 / ( Fcpu / 214 / 16 ) = 65.5s, Fosc=16KHz@3V 1 / ( Fcpu / 28 / 16 ) = 1s, Fosc=16KHz@3V 1 / ( 16K / 512 / 16 ) ~ 0.5s @3V Bit6 Bit7 Table 8-1. Watchdog timer overflow timetable SONiX TECHNOLOGY CO., LTD Page 53 Revision 0.5 Preliminary Note: The watch dog timer can be enabled or disabled by the code option. SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Example: An operation of watchdog timer is as following. To clear the watchdog timer's counter in the top of the main routine of the program. Main: B0BSET . CALL CALL . . . JMP FWDRST . SUB1 SUB2 . . . MAIN ; Clear the watchdog timer's counter. T0M Register T0M initial value = xxxx 000x 0D8H T0M Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TC1X8 R/W Bit 2 TC0X8 R/W Bit 1 TC0GN R/W Bit 0 - Bit3 TC1X8: Multiple TC1 timer speed eight times. Refer TC1M register for detailed information. 0 = Disable 1 = Enable TC0X8: Multiple TC0 timer speed eight times. Refer TC0M register for detailed information. 0 = Disable 1 = Enable TC0GN: Enable TC0 green mode wakeup function 0 = Disable 1 = Enable Bit2 Bit0 SONiX TECHNOLOGY CO., LTD Page 54 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TIMER COUNTER 0 (TC0) OVERVIEW The timer counter 0 (TC0) is used to generate an interrupt request when a specified time interval has elapsed. TC0 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC0R) into which you write the counter reference value, and an 8-bit counter register (TC0C) whose value is automatically incremented by counter logic. Internal P5.4 I/O circuit Buzzer TC0out Aload0 TC0R reload data buffer Auto. reload O 2 P5.4 R /2(8-TC0Rate) TC0CKS Fcpu TC0enb load Compare S PWM PWM0OUT TC0C 8-bit binary counter INT0 (schmitter trigger) CPUM0 TC0 Time out Figure 8-1. TC0 Block Diagram The main purposes of the TC0 timer counter is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ0 pin (P5.4). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM0OUT pin (P5.4). SONiX TECHNOLOGY CO., LTD Page 55 Revision 0.5 Preliminary TC0M MODE REGISTER SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The TC0M is the timer counter mode register, which is an 8-bit read/write register. By loading different value into the TC0M register, users can modify the timer counter clock frequency dynamically when program executing. Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 and TC0X8 bits of T0M register. If TC0X8=1 the TC0 will faster 8 times than TC0X8=0 (Initial value). The bit7 of TC0M named TC0ENB is the control bit to start TC0 timer. TC0M initial value = 0000 0000 0DAH TC0M Bit 7 TC0ENB R/W Bit 6 Bit 5 Bit 4 TC0RATE2 TC0RATE1 TC0RATE0 R/W R/W R/W Bit 3 TC0CKS R/W Bit 2 ALOAD0 R/W Bit 1 TC0OUT R/W Bit 0 PWM0OUT R/W Bit7 TC0ENB: TC0 counter/BZ0/PWM0OUT enable bit. 0 = disable, 1 = enable. TC0RATE[2:0]: TC0 clock source selection bits. TC0X8 is bit 2 of T0M register. TC0RATE [2:0] 000 001 ... 110 111 TC0 Clock Source TC0X8 = 0 TC0X8 = 1 Fcpu/256 = Fosc/1024 Fosc/128 Fcpu/128 = Fosc/512 Fosc/64 ... ... Fcpu/4 = Fosc/16 Fosc/2 Fcpu/2 = Fosc/8 Fosc Bit [6:4] Note: Fcpu = Fosc / 4 Bit3 TC0CKS: TC0 clock source select bit. 0 = Fcpu, 1 = External clock comes from INT0/P0.0 pin. ALOAD0: TC0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC0OUT: TC0 time-out toggle signal output control bit. 0 = to disable TC0 signal output and to enable P5.4's I/O function, 1 = to enable TC0's signal output and to disable P5.4's I/O function. (Auto-disable the PWM0OUT function.) PWM0OUT: TC0's PWM output control bit. 0 = to disable the PWM output, 1 = to enable the PWM output (The TC0OUT control bit must = 0 ) Note: When TC0CKS=1, TC0 became an external event counter. No more P0.0 interrupt request will be raised. (P0.0IRQ will be always 0) Bit2 Bit1 Bit0 SONiX TECHNOLOGY CO., LTD Page 56 Revision 0.5 Preliminary TC0C COUNTING REGISTER SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC0C is an 8-bit counter register for the timer counter (TC0). TC0C must be reset whenever the TC0ENB is set "1" to start the timer counter. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to "0FFH", it is will be cleared to "00H" in next clock and an overflow is generated. Under TC0 interrupt service request (TC0IEN) enable condition, the TC0 interrupt request flag will be set "1" and the system executes the interrupt service routine. TC0C initial value = xxxx xxxx 0DBH TC0C Bit 7 TC0C7 R/W Bit 6 TC0C6 R/W Bit 5 TC0C5 R/W Bit 4 TC0C4 R/W Bit 3 TC0C3 R/W Bit 2 TC0C2 R/W Bit 1 TC0C1 R/W Bit 0 TC0C0 R/W TC0 Overflow Time TC0 rate is determinate by TC0Rate and Code Option TC0_Counter, TC0Rate can set TC0 clock frequency and TC0_Counter set TC0 became 8-bit, 6-bit, 5-bit or 4-bit counter. The equation of TC0C initial value is as following. TC0C initial value = N - (TC0 interrupt interval time * input clock) Which N is determinate by code option: TC0_Counter TC0_Counter N Max. TC0C value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 Note: TheTC0C must small or equal than Max. TC0 value. Example: To set 10ms interval time for TC0 interrupt at Fosc = 3.58MHz TC0C value (74H) = 256 - (10ms * fcpu/64) (TC0RATE=010, TC0_Counter=8-bit, TC0X8=0) TC0C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (0.01 * 3.58 * 106 / 4 / 64) = 116 = 74H Example: To set 1.25ms interval time for TC0 interrupt at Fosc = 3.58MHz TC0C value (74H) = 256 - (10ms * fcpu/64) (TC0RATE=010, TC0_Counter=8-bit, TC0X8=1) TC0C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (1.25ms * 3.58 * 106 / 32) = 256 - (0.00125 * 3.58 * 106 / 32) = 116 = 74H Example: To set 1ms interval time for TC0 interrupt at Fosc = 3.58MHz TC0C value (32H) = 64 - (1ms * fcpu/64) (TC0RATE=010, TC0_COunter=6-bit, TC0X8=0) TC0C initial value = 64 - (TC0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 106 / 4 / 64) = 64 - (0.001 * 3.58 * 106 / 4 / 64) = 64 - 14 = 32H SONiX TECHNOLOGY CO., LTD Page 57 Revision 0.5 Preliminary TC0_Counter=8-bit, TC0X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC0RATE TC0CLOCK Max overflow interval One step = max/256 000 Fcpu/256 73.2 ms 286us 001 Fcpu/128 36.6 ms 143us 010 Fcpu/64 18.3 ms 71.5us 011 Fcpu/32 9.15 ms 35.8us 100 Fcpu/16 4.57 ms 17.9us 101 Fcpu/8 2.28 ms 8.94us 110 Fcpu/4 1.14 ms 4.47us 111 Fcpu/2 0.57 ms 2.23us TC0_Counter=6-bit , TC0X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC0RATE TC0CLOCK Max overflow interval One step = max/64 000 Fcpu/256 18.3 ms 286us 001 Fcpu/128 9.15 ms 143us 010 Fcpu/64 4.57 ms 71.5us 011 Fcpu/32 2.28 ms 35.8us 100 Fcpu/16 1.14 ms 17.9us 101 Fcpu/8 0.57 ms 8.94us 110 Fcpu/4 0.285 ms 4.47us 111 Fcpu/2 0.143 ms 2.23us TC0_Counter=5-bit, TC0X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC0RATE TC0CLOCK Max overflow interval One step = max/32 000 Fcpu/256 9.15 ms 286us 001 Fcpu/128 4.57 ms 143us 010 Fcpu/64 2.28 ms 71.5us 011 Fcpu/32 1.14 ms 35.8us 100 Fcpu/16 0.57 ms 17.9us 101 Fcpu/8 0.285 ms 8.94us 110 Fcpu/4 0.143 ms 4.47us 111 Fcpu/2 71.25 us 2.23us TC0_Counter=4-bit, TC0X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC0RATE TC0CLOCK Max overflow interval One step = max/16 000 Fcpu/256 4.57 ms 286us 001 Fcpu/128 2.28 ms 143us 010 Fcpu/64 1.14 ms 71.5us 011 Fcpu/32 0.57 ms 35.8us 100 Fcpu/16 0.285 ms 17.9us 101 Fcpu/8 0.143 ms 8.94us 110 Fcpu/4 71.25 us 4.47us 111 Fcpu/2 35.63 us 2.23us SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Low speed mode (Fosc = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/64 2000 ms 31.25 ms 1000 ms 15.63 ms 500 ms 7.8 ms 250 ms 3.9 ms 125 ms 1.95 ms 62.5 ms 0.98 ms 31.25 ms 0.49 ms 15.63 ms 0.24 ms Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/32 1000 ms 31.25 ms 500 ms 15.63 ms 250 ms 7.8 ms 125 ms 3.9 ms 62.5 ms 1.95 ms 31.25 ms 0.98 ms 15.63 ms 0.49 ms 7.81 ms 0.24 ms Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/16 500 ms 31.25 ms 250 ms 15.63 ms 125 ms 7.8 ms 62.5 ms 3.9 ms 31.25 ms 1.95 ms 15.63 ms 0.98 ms 7.81 ms 0.49 ms 3.91 ms 0.24 ms SONiX TECHNOLOGY CO., LTD Page 58 Revision 0.5 Preliminary TC0_Counter=8-bit, TC0X8=1 High speed mode (Fosc = 3.58MHz) TC0RATE TC0CLOCK Max overflow interval One step = max/256 000 Fosc/128 9.153 ms 35.754us 001 Fosc/64 4.58 ms 17.877us 010 Fosc/32 2.29 ms 8.939us 011 Fosc/16 1.14 ms 4.470us 100 Fosc/8 0.57 ms 2.235us 101 Fosc/4 0.29 ms 1.117us 110 Fosc/2 0.14 ms 0.587us 111 Fosc 71.5 us 0.279us TC0_Counter=6-bit , TC0X8=1 High speed mode (Fosc = 3.58MHz) TC0RATE TC0CLOCK Max overflow interval One step = max/64 000 Fosc/128 2.29 ms 35.754us 001 Fosc/64 1.14 ms 17.877us 010 Fosc/32 0.57 ms 8.939us 011 Fosc/16 0.29 ms 4.470us 100 Fosc/8 0.14 ms 2.235us 101 Fosc/4 71.5 us 1.117us 110 Fosc/2 35.75 us 0.587us 111 Fosc 17.875 us 0.279us TC0_Counter=5-bit, TC0X8=1 High speed mode (Fosc = 3.58MHz) TC0RATE TC0CLOCK Max overflow interval One step = max/32 000 Fosc/128 1.14 ms 35.754us 001 Fosc/64 0.57 ms 17.877us 010 Fosc/32 0.29 ms 8.939us 011 Fosc/16 0.14 ms 4.470us 100 Fosc/8 71.5 us 2.235us 101 Fosc/4 35.75 us 1.117us 110 Fosc/2 17.875 us 0.587us 111 Fosc 8.936 us 0.279us TC0_Counter=4-bit, TC0X8=1 High speed mode (Fosc = 3.58MHz) TC0RATE TC0CLOCK Max overflow interval One step = max/16 000 Fosc/128 0.57 ms 35.754us 001 Fosc/64 0.29 ms 17.877us 010 Fosc/32 0.14 ms 8.939us 011 Fosc/16 71.5 us 4.470us 100 Fosc/8 35.75 us 2.235us 101 Fosc/4 17.875 us 1.117us 110 Fosc/2 8.936 us 0.587us 111 Fosc 4.468 us 0.279us SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/256 1000 ms 3.91 ms 500 ms 1.95 ms 250 ms 0.977 ms 125 ms 0.488 ms 62.5 ms 0.244 ms 31.25 ms 0.122 ms 15.63 ms 0.061 ms 7.81ms 0.03 ms Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/64 250 ms 3.91 ms 125 ms 1.95 ms 62.5 ms 0.977 ms 31.25 ms 0.488 ms 15.63 ms 0.244 ms 7.81ms 0.122 ms 3.905 ms 0.061 ms 1.953 ms 0.03 ms Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/32 125 ms 3.91 ms 62.5 ms 1.95 ms 31.25 ms 0.977 ms 15.63 ms 0.488 ms 7.81ms 0.244 ms 3.905 ms 0.122 ms 1.953 ms 0.061 ms 0.976 ms 0.03 ms Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/16 62.5 ms 3.91 ms 31.25 ms 1.95 ms 15.63 ms 0.977 ms 7.81ms 0.488 ms 3.905 ms 0.244 ms 1.953 ms 0.122 ms 0.976 ms 0.061 ms 0.488 ms 0.03 ms Table 8-2. The Timing Table of Timer Counter TC0 SONiX TECHNOLOGY CO., LTD Page 59 Revision 0.5 Preliminary TC0R AUTO-LOAD REGISTER SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC0R is an 8-bit register for the TC0 auto-reload function. TC0R's value applies to TC0OUT and PWM0OUT functions. Under TC0OUT application, users must enable and set the TC0R register. The main purpose of TC0R is as following. Store the auto-reload value and set into TC0C when the TC0C overflow. (ALOAD0 = 1). Store the duty value of PWM0OUT function. TC0R initial value = xxxx xxxx 0CDH TC0R Bit 7 TC0R7 W Bit 6 TC0R6 W Bit 5 TC0R5 W Bit 4 TC0R4 W Bit 3 TC0R3 W Bit 2 TC0R2 W Bit 1 TC0R1 W Bit 0 TC0R0 W The equation of TC0R initial value is like TC0C as following. TC0R initial value = N - (TC0 interrupt interval time * input clock) Which N is determinate by code option: TC0_Counter TC0_Counter N Max. TC0R value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 Note: TheTC0R must small or equal than Max. TC0R value. Note: The TC0R is write-only register can't be process by INCMS, DECMS instructions. SONiX TECHNOLOGY CO., LTD Page 60 Revision 0.5 Preliminary TC0 TIMER COUNTER OPERATION SEQUENCE The TC0 timer counter's sequence of operation can be following. SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Set the TC0C initial value to setup the interval time. Set the TC0ENB to be "1" to enable TC0 timer counter. TC0C is incremented by one with each clock pulse which frequency is corresponding to TC0M selection. TC0C overflow when TC0C from FFH to 00H. When TC0C overflow occur, the TC0IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the TC0C value and resume the TC0 timer operation. Example: Setup the TC0M and TC0C without auto-reload function. (TC0_Counter=8-bit) B0BCLR B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET FTC0X8 FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A FTC0IEN FTC0IRQ FTC0ENB ; ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = Fcpu / 64 ; To set TC0C initial value = 74H ;(To set TC0 interval = 10 ms) ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer Example: Setup the TC0M and TC0C with auto-reload function. (TC0_Counter=8-bit) B0BCLR B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC0X8 FTC0IEN FTC0ENB A,#20H TC0M,A A,#74H TC0C,A TC0R,A FTC0IEN FTC0IRQ FTC0ENB ALOAD0 ; To select TC0=Fcpu/2 as clock source ; To disable TC0 interrupt service ; To disable TC0 timer ; ; To set TC0 clock = Fcpu / 64 ; To set TC0C initial value = 74H ; (To set TC0 interval = 10 ms) ; To set TC0R auto-reload register ; To enable TC0 interrupt service ; To clear TC0 interrupt request ; To enable TC0 timer ; To enable TC0 auto-reload function. SONiX TECHNOLOGY CO., LTD Page 61 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Example: TC0 interrupt service routine without auto-reload function. (TC0_Counter=8-bit) ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: B0MOV B0MOV B0XCH RETI A, PFLAGBUF PFLAG, A A, ACCBUF A, ACCBUF A, PFLAG PFLAGBUF, A FTC0IRQ EXIT_INT FTC0IRQ A,#74H TC0C,A . . EXIT_INT . . ; Store ACC value. 8 INT_SERVICE ; Interrupt vector ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; Reload TC0C ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector ; Restore ACC value. ; Exit interrupt vector Example: TC0 interrupt service routine with auto-reload. (TC0_Counter=8-bit) ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV B0BTS1 JMP B0BCLR . . JMP . . EXIT_INT: B0MOV B0MOV B0XCH RETI A, PFLAGBUF PFLAG, A A, ACCBUF A, ACCBUF A, PFLAG PFLAGBUF, A FTC0IRQ EXIT_INT FTC0IRQ . . EXIT_INT . . ; Store ACC value. 8 INT_SERVICE ; Interrupt vector ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; TC0 interrupt service routine ; End of TC0 interrupt service routine and exit interrupt vector ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 62 Revision 0.5 Preliminary TC0 CLOCK FREQUENCY OUTPUT (BUZZER) SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC0 timer counter provides a frequency output function. By setting the TC0 clock frequency, the clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0 output signal divides by 2. The TC0 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency. Figure 8-2. The TC0OUT Pulse Frequency Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The TC0OUT frequency is 1KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 2KHz. The TC0 clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110, TC0C = TC0R = 131, TC0X8 = 0, TC0_Counter=8-bit B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET FTC0X8 A,#01100000B TC0M,A A,#131 TC0C,A TC0R,A FTC0OUT FALOAD0 FTC0ENB ; Set TC0X8 to 0 ; Set the TC0 rate to Fcpu/4 ; Set the auto-reload reference value ; Enable TC0 output to P5.4 and disable P5.4 I/O function ; Enable TC0 auto-reload function ; Enable TC0 timer SONiX TECHNOLOGY CO., LTD Page 63 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC0OUT FREQUENCY TABLE Fosc = 4MHz, TC0 Rate = Fcpu/8, TC0_Counter=8-bit, TC0X8=0 TC0R TC0OUT (KHz) 0.2441 0.2451 0.2461 0.2470 0.2480 0.2490 0.2500 0.2510 0.2520 0.2530 0.2541 0.2551 0.2561 0.2572 0.2583 0.2593 0.2604 0.2615 0.2626 0.2637 0.2648 0.2660 0.2671 0.2682 0.2694 0.2706 0.2717 0.2729 0.2741 0.2753 0.2765 0.2778 0.2790 0.2803 0.2815 0.2828 0.2841 0.2854 0.2867 0.2880 0.2894 0.2907 0.2921 0.2934 0.2948 0.2962 0.2976 0.2990 0.3005 0.3019 0.3034 0.3049 0.3064 0.3079 0.3094 0.3109 TC0R TC0OUT (KHz) 0.3125 0.3141 0.3157 0.3173 0.3189 0.3205 0.3222 0.3238 0.3255 0.3272 0.3289 0.3307 0.3324 0.3342 0.3360 0.3378 0.3397 0.3415 0.3434 0.3453 0.3472 0.3492 0.3511 0.3531 0.3551 0.3571 0.3592 0.3613 0.3634 0.3655 0.3676 0.3698 0.3720 0.3743 0.3765 0.3788 0.3811 0.3834 0.3858 0.3882 0.3906 0.3931 0.3956 0.3981 0.4006 0.4032 0.4058 0.4085 0.4112 0.4139 0.4167 0.4195 0.4223 0.4252 0.4281 0.4310 TC0R TC0OUT (KHz) 0.4340 0.4371 0.4401 0.4433 0.4464 0.4496 0.4529 0.4562 0.4596 0.4630 0.4664 0.4699 0.4735 0.4771 0.4808 0.4845 0.4883 0.4921 0.4960 0.5000 0.5040 0.5081 0.5123 0.5165 0.5208 0.5252 0.5297 0.5342 0.5388 0.5435 0.5482 0.5531 0.5580 0.5631 0.5682 0.5734 0.5787 0.5841 0.5896 0.5952 0.6010 0.6068 0.6127 0.6188 0.6250 0.6313 0.6378 0.6443 0.6510 0.6579 0.6649 0.6720 0.6793 0.6868 0.6944 0.7022 TC0R TC0OUT (KHz) 0.7102 0.7184 0.7267 0.7353 0.7440 0.7530 0.7622 0.7716 0.7813 0.7911 0.8013 0.8117 0.8224 0.8333 0.8446 0.8562 0.8681 0.8803 0.8929 0.9058 0.9191 0.9328 0.9470 0.9615 0.9766 0.9921 1.0081 1.0246 1.0417 1.0593 1.0776 1.0965 1.1161 1.1364 1.1574 1.1792 1.2019 1.2255 1.2500 1.2755 1.3021 1.3298 1.3587 1.3889 1.4205 1.4535 1.4881 1.5244 1.5625 1.6026 1.6447 1.6892 1.7361 1.7857 1.8382 1.8939 TC0R TC0OUT (KHz) 1.9531 2.0161 2.0833 2.1552 2.2321 2.3148 2.4038 2.5000 2.6042 2.7174 2.8409 2.9762 3.1250 3.2895 3.4722 3.6765 3.9063 4.1667 4.4643 4.8077 5.2083 5.6818 6.2500 6.9444 7.8125 8.9286 10.4167 12.5000 15.6250 20.8333 31.2500 62.5000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Table 8-3. TC0OUT Frequency Table for Fosc = 4MHz, TC0 Rate = Fcpu/8 SONiX TECHNOLOGY CO., LTD Page 64 Revision 0.5 Preliminary Fosc = 16MHz, TC0 Rate = Fcpu/8, TC0_Counter=8-bit TC0R TC0OUT (KHz) 0.9766 0.9804 0.9843 0.9881 0.9921 0.9960 1.0000 1.0040 1.0081 1.0121 1.0163 1.0204 1.0246 1.0288 1.0331 1.0373 1.0417 1.0460 1.0504 1.0549 1.0593 1.0638 1.0684 1.0730 1.0776 1.0823 1.0870 1.0917 1.0965 1.1013 1.1062 1.1111 1.1161 1.1211 1.1261 1.1312 1.1364 1.1416 1.1468 1.1521 1.1574 1.1628 1.1682 1.1737 1.1792 1.1848 1.1905 1.1962 1.2019 1.2077 1.2136 1.2195 1.2255 1.2315 1.2376 1.2438 TC0R TC0OUT (KHz) 1.2500 1.2563 1.2626 1.2690 1.2755 1.2821 1.2887 1.2953 1.3021 1.3089 1.3158 1.3228 1.3298 1.3369 1.3441 1.3514 1.3587 1.3661 1.3736 1.3812 1.3889 1.3966 1.4045 1.4124 1.4205 1.4286 1.4368 1.4451 1.4535 1.4620 1.4706 1.4793 1.4881 1.4970 1.5060 1.5152 1.5244 1.5337 1.5432 1.5528 1.5625 1.5723 1.5823 1.5924 1.6026 1.6129 1.6234 1.6340 1.6447 1.6556 1.6667 1.6779 1.6892 1.7007 1.7123 1.7241 TC0R TC0OUT (KHz) 1.7361 1.7483 1.7606 1.7730 1.7857 1.7986 1.8116 1.8248 1.8382 1.8519 1.8657 1.8797 1.8939 1.9084 1.9231 1.9380 1.9531 1.9685 1.9841 2.0000 2.0161 2.0325 2.0492 2.0661 2.0833 2.1008 2.1186 2.1368 2.1552 2.1739 2.1930 2.2124 2.2321 2.2523 2.2727 2.2936 2.3148 2.3364 2.3585 2.3810 2.4038 2.4272 2.4510 2.4752 2.5000 2.5253 2.5510 2.5773 2.6042 2.6316 2.6596 2.6882 2.7174 2.7473 2.7778 2.8090 TC0R SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 TC0OUT (KHz) 2.8409 2.8736 2.9070 2.9412 2.9762 3.0120 3.0488 3.0864 3.1250 3.1646 3.2051 3.2468 3.2895 3.3333 3.3784 3.4247 3.4722 3.5211 3.5714 3.6232 3.6765 3.7313 3.7879 3.8462 3.9063 3.9683 4.0323 4.0984 4.1667 4.2373 4.3103 4.3860 4.4643 4.5455 4.6296 4.7170 4.8077 4.9020 5.0000 5.1020 5.2083 5.3191 5.4348 5.5556 5.6818 5.8140 5.9524 6.0976 6.2500 6.4103 6.5789 6.7568 6.9444 7.1429 7.3529 7.5758 TC0R 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 TC0OUT (KHz) 7.8125 8.0645 8.3333 8.6207 8.9286 9.2593 9.6154 10.0000 10.4167 10.8696 11.3636 11.9048 12.5000 13.1579 13.8889 14.7059 15.6250 16.6667 17.8571 19.2308 20.8333 22.7273 25.0000 27.7778 31.2500 35.7143 41.6667 50.0000 62.5000 83.3333 125.0000 250.0000 Table 8-4TC0OUT Frequency Table for Fosc = 16MHz, TC0 Rate = Fcpu/8 SONiX TECHNOLOGY CO., LTD Page 65 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TIMER COUNTER 1 (TC1) OVERVIEW The timer counter 1 (TC1) is used to generate an interrupt request when a specified time interval has elapsed. TC1 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC1R) into which you write the counter Aload1 TC1R reload data buffer Internal P5.3 I/O circuit Buzzer TC1out Auto. reload O 2 P5.3 R Compare PWM PWM1OUT TC1enb load S fcpu /2(8-TC1Rate) CPUM0 TC1C 8-bit binary counter TC1 Time out reference value, and an 8-bit counter register (TC1C) whose value is automatically incremented by counter logic. Figure 8-3. Timer Counter TC1 Block Diagram The main purposes of the TC1 timer is as following. 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency. Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3). PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1OUT pin (P5.3). SONiX TECHNOLOGY CO., LTD Page 66 Revision 0.5 Preliminary TC1M MODE REGISTER SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC The TC1M is the timer mode register, which is an 8-bit read/write register. By loading different value into the TC1M register, users can modify the timer counter clock frequency dynamically when program executing. Eight rates for TC1 timer can be selected by TC1RATE0 ~ TC1RATE2 and TC1X8 bits of T0M register. If TC1X8=1 the TC1 will faster 8 times than TC1X8=0 (Initial value). The bit7 of TC1M named TC1ENB is the control bit to start TC1 timer. TC1M initial value = 0000 0000 0DCH TC1M Bit 7 TC1ENB R/W Bit 6 Bit 5 Bit 4 TC1RATE2 TC1RATE1 TC1RATE0 R/W R/W R/W Bit 3 0 Bit 2 ALOAD1 R/W Bit 1 TC1OUT R/W Bit 0 PWM1OUT R/W Bit7 TC1ENB: TC1 counter/BZ1/PWM1OUT enable bit. 0 = disable, 1 = enable. TC1RATE[2:0]: TC1 clock source selection bits. TC1X8 is bit 3 of T0M register. TC1 Clock Source TC1X8 = 0 TC1X8 = 1 000 Fcpu/256 = Fosc/1024 Fosc/128 001 Fcpu/128 = Fosc/512 Fosc/64 ... ... ... 110 Fcpu/4 = Fosc/16 Fosc/2 111 Fcpu/2 = Fosc/8 Fosc Note: Fcpu = Fosc / 4 TC1RATE [2:0] Bit[6:4] Bit2 ALOAD1: TC1 auto-reload function control bit. 0 = none auto-reload 1 = auto-reload. TC01UT: TC1 time-out toggle signal output control bit. 0 = to disable TC1 signal output and to enable P5.3's I/O function, 1 = to enable TC1's signal output and to disable P5.3's I/O function. (Auto-disable the PWM0OUT function.) PWM1OUT: TC1's PWM output control bit. 0 = to disable the PWM output, 1 = to enable the PWM output (The TC1OUT control bit must = 0) Bit1 Bit0 Note: TC1 doesn't support event counter mode because SN8P1702A and SN8P1703A hasn't P0.1 for TC1 event counter clock input. Note: Bit3 must set to "0". SONiX TECHNOLOGY CO., LTD Page 67 Revision 0.5 Preliminary TC1C COUNTING REGISTER SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC1C is an 8-bit counter register for the timer counter (TC1). TC1C must be reset whenever the TC1ENB is set "1" to start the timer. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to "0FFH", it is will be cleared to "00H" in next clock and an overflow is generated. Under TC1 interrupt service request (TC1IEN) enable condition, the TC1 interrupt request flag will be set "1" and the system executes the interrupt service routine. TC1C initial value = xxxx xxxx 0DDH TC1C Bit 7 TC1C7 R/W Bit 6 TC1C6 R/W Bit 5 TC1C5 R/W Bit 4 TC1C4 R/W Bit 3 TC1C3 R/W Bit 2 TC1C2 R/W Bit 1 TC1C1 R/W Bit 0 TC1C0 R/W TC1 Overflow Time TC1 rate is determinate by TC1Rate and Code Option TC1_Counter, TC1Rate can set TC1 clock frequency from Fcpu and TC1_Counter set TC1 became 8-bit, 6-bit, 5-bit or 4-bit counter. The equation of TC1C initial value is as following. TC1C initial value = N - (TC1 interrupt interval time * input clock) Which N is determinate by code option: TC1_Counter TC1_Counter N Max. TC1C value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 Note: TheTC1C must small or equal than Max. TC1 value. Example: To set 10ms interval time for TC1 interrupt at Fosc = 3.58MHz TC1C value (74H) = 256 - (10ms * fcpu/64) (TC1RATE=010, TC1_Counter=8-bit, TC1X8=0) TC1C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (10ms * 3.58 * 106 / 4 / 64) = 256 - (0.01 * 3.58 * 106 / 4 / 64) = 116 = 74H Example: To set 1.25ms interval time for TC1 interrupt at Fosc = 3.58MHz TC1C value (74H) = 256 - (10ms * fcpu/64) (TC1RATE=010, TC1_Counter=8-bit, TC1X8=1) TC1C initial value = 256 - (TC0 interrupt interval time * input clock) = 256 - (1.25ms * 3.58 * 106 / 32) = 256 - (0.00125 * 3.58 * 106 / 32) = 116 = 74H Example: To set 1ms interval time for TC1 interrupt at Fosc = 3.58MHz TC1C value (32H) = 64 - (1ms * fcpu/64) (TC1RATE=010, TC1_COunter=6-bit, TC1X8=0) TC1C initial value = 64 - (TC0 interrupt interval time * input clock) = 64 - (1ms * 3.58 * 106 / 4 / 64) = 64 - (0.001 * 3.58 * 106 / 4 / 64) = 64 - 14 = 32H SONiX TECHNOLOGY CO., LTD Page 68 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC1_Counter=8-bit, TC1X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC1RATE TC1CLOCK Max overflow interval One step = max/256 000 Fcpu/256 73.2 ms 286us 001 Fcpu/128 36.6 ms 143us 010 Fcpu/64 18.3 ms 71.5us 011 Fcpu/32 9.15 ms 35.8us 100 Fcpu/16 4.57 ms 17.9us 101 Fcpu/8 2.28 ms 8.94us 110 Fcpu/4 1.14 ms 4.47us 111 Fcpu/2 0.57 ms 2.23us TC1_Counter=6-bit , TC1X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC1RATE TC1CLOCK Max overflow interval One step = max/64 000 Fcpu/256 18.3 ms 286us 001 Fcpu/128 9.15 ms 143us 010 Fcpu/64 4.57 ms 71.5us 011 Fcpu/32 2.28 ms 35.8us 100 Fcpu/16 1.14 ms 17.9us 101 Fcpu/8 0.57 ms 8.94us 110 Fcpu/4 0.285 ms 4.47us 111 Fcpu/2 0.143 ms 2.23us TC1_Counter=5-bit, TC1X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC1RATE TC1CLOCK Max overflow interval One step = max/32 000 Fcpu/256 9.15 ms 286us 001 Fcpu/128 4.57 ms 143us 010 Fcpu/64 2.28 ms 71.5us 011 Fcpu/32 1.14 ms 35.8us 100 Fcpu/16 0.57 ms 17.9us 101 Fcpu/8 0.285 ms 8.94us 110 Fcpu/4 0.143 ms 4.47us 111 Fcpu/2 71.25 us 2.23us TC1_Counter=4-bit, TC1X8=0 High speed mode (Fcpu = 3.58MHz / 4) TC1RATE TC1CLOCK Max overflow interval One step = max/16 000 Fcpu/256 4.57 ms 286us 001 Fcpu/128 2.28 ms 143us 010 Fcpu/64 1.14 ms 71.5us 011 Fcpu/32 0.57 ms 35.8us 100 Fcpu/16 0.285 ms 17.9us 101 Fcpu/8 0.143 ms 8.94us 110 Fcpu/4 71.25 us 4.47us 111 Fcpu/2 35.63 us 2.23us Low speed mode (Fosc = 32768Hz / 4) Max overflow interval One step = max/256 8000 ms 31.25 ms 4000 ms 15.63 ms 2000 ms 7.8 ms 1000 ms 3.9 ms 500 ms 1.95 ms 250 ms 0.98 ms 125 ms 0.49 ms 62.5 ms 0.24 ms Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/64 2000 ms 31.25 ms 1000 ms 15.63 ms 500 ms 7.8 ms 250 ms 3.9 ms 125 ms 1.95 ms 62.5 ms 0.98 ms 31.25 ms 0.49 ms 15.63 ms 0.24 ms Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/32 1000 ms 31.25 ms 500 ms 15.63 ms 250 ms 7.8 ms 125 ms 3.9 ms 62.5 ms 1.95 ms 31.25 ms 0.98 ms 15.63 ms 0.49 ms 7.81 ms 0.24 ms Low speed mode (Fcpu = 32768Hz / 4) Max overflow interval One step = max/16 500 ms 31.25 ms 250 ms 15.63 ms 125 ms 7.8 ms 62.5 ms 3.9 ms 31.25 ms 1.95 ms 15.63 ms 0.98 ms 7.81 ms 0.49 ms 3.91 ms 0.24 ms SONiX TECHNOLOGY CO., LTD Page 69 Revision 0.5 Preliminary TC1_Counter=8-bit, TC1X8=1 High speed mode (Fosc = 3.58MHz) TC1RATE TC1CLOCK Max overflow interval One step = max/256 000 Fosc/128 9.153 ms 35.754us 001 Fosc/64 4.58 ms 17.877us 010 Fosc/32 2.29 ms 8.939us 011 Fosc/16 1.14 ms 4.470us 100 Fosc/8 0.57 ms 2.235us 101 Fosc/4 0.29 ms 1.117us 110 Fosc/2 0.14 ms 0.587us 111 Fosc 71.5 us 0.279us TC1_Counter=6-bit , TC1X8=1 High speed mode (Fosc = 3.58MHz) TC1RATE TC1CLOCK Max overflow interval One step = max/64 000 Fosc/128 2.29 ms 35.754us 001 Fosc/64 1.14 ms 17.877us 010 Fosc/32 0.57 ms 8.939us 011 Fosc/16 0.29 ms 4.470us 100 Fosc/8 0.14 ms 2.235us 101 Fosc/4 71.5 us 1.117us 110 Fosc/2 35.75 us 0.587us 111 Fosc 17.875 us 0.279us TC1_Counter=5-bit, TC1X8=1 High speed mode (Fosc = 3.58MHz) TC1RATE TC1CLOCK Max overflow interval One step = max/32 000 Fosc/128 1.14 ms 35.754us 001 Fosc/64 0.57 ms 17.877us 010 Fosc/32 0.29 ms 8.939us 011 Fosc/16 0.14 ms 4.470us 100 Fosc/8 71.5 us 2.235us 101 Fosc/4 35.75 us 1.117us 110 Fosc/2 17.875 us 0.587us 111 Fosc 8.936 us 0.279us TC1_Counter=4-bit, TC1X8=1 High speed mode (Fosc = 3.58MHz) TC1RATE TC1CLOCK Max overflow interval One step = max/16 000 Fosc/128 0.57 ms 35.754us 001 Fosc/64 0.29 ms 17.877us 010 Fosc/32 0.14 ms 8.939us 011 Fosc/16 71.5 us 4.470us 100 Fosc/8 35.75 us 2.235us 101 Fosc/4 17.875 us 1.117us 110 Fosc/2 8.936 us 0.587us 111 Fosc 4.468 us 0.279us SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/256 1000 ms 3.91 ms 500 ms 1.95 ms 250 ms 0.977 ms 125 ms 0.488 ms 62.5 ms 0.244 ms 31.25 ms 0.122 ms 15.63 ms 0.061 ms 7.81ms 0.03 ms Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/64 250 ms 3.91 ms 125 ms 1.95 ms 62.5 ms 0.977 ms 31.25 ms 0.488 ms 15.63 ms 0.244 ms 7.81ms 0.122 ms 3.905 ms 0.061 ms 1.953 ms 0.03 ms Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/32 125 ms 3.91 ms 62.5 ms 1.95 ms 31.25 ms 0.977 ms 15.63 ms 0.488 ms 7.81ms 0.244 ms 3.905 ms 0.122 ms 1.953 ms 0.061 ms 0.976 ms 0.03 ms Low speed mode (Fosc = 32768Hz) Max overflow interval One step = max/16 62.5 ms 3.91 ms 31.25 ms 1.95 ms 15.63 ms 0.977 ms 7.81ms 0.488 ms 3.905 ms 0.244 ms 1.953 ms 0.122 ms 0.976 ms 0.061 ms 0.488 ms 0.03 ms Table 8-5. The Timing Table of Timer Counter TC1 SONiX TECHNOLOGY CO., LTD Page 70 Revision 0.5 Preliminary TC1R AUTO-LOAD REGISTER SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC1R is an 8-bit register for the TC1 auto-reload function. TC1R's value applies to TC1OUT and PWM1OUT functions. Under TC1OUT application, users must enable and set the TC1R register. The main purpose of TC1R is as following. Store the auto-reload value and set into TC1C when the TC1C overflow. (ALOAD1 = 1). Store the duty value of PWM1OUT function. TC1R initial value = xxxx xxxx 0DEH TC1R Bit 7 TC1R7 W Bit 6 TC1R6 W Bit 5 TC1R5 W Bit 4 TC1R4 W Bit 3 TC1R3 W Bit 2 TC1R2 W Bit 1 TC1R1 W Bit 0 TC1R0 W The equation of TC1R initial value is like TC1C as following. TC1R initial value = N - (TC1 interrupt interval time * input clock) Which N is determinate by code option: TC1_Counter TC1_Counter N Max. TC1R value 8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15 Note: TheTC1R must small or equal than Max. TC1R value. Note: The TC1R is write-only register can't be process by INCMS, DECMS instructions. SONiX TECHNOLOGY CO., LTD Page 71 Revision 0.5 Preliminary TC1 TIMER COUNTER OPERATION SEQUENCE The TC1 timer's sequence of operation can be following. SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Set the TC1C initial value to setup the interval time. Set the TC1ENB to be "1" to enable TC1 timer counter. TC1C is incremented by one with each clock pulse which frequency is corresponding to TC1M selection. TC1C overflow if TC1C from FFH to 00H. When TC1C overflow occur, the TC1IRQ flag is set to be "1" by hardware. Execute the interrupt service routine. Users reset the TC1C value and resume the TC1 timer operation. Example: Setup the TC1M and TC1C without auto-reload function.(TC1_Counter=8-bit, TC1X8=0) B0BCLR B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET FTC1X8 FTC1IEN FTC1ENB A,#20H TC1M,A A,#74H TC1C,A FTC1IEN FTC1IRQ FTC1ENB ; ; To disable TC1 interrupt service ; To disable TC1 timer ; ; To set TC1 clock = Fcpu / 64 ; To set TC1C initial value = 74H ;(To set TC1 interval = 10 ms) ; To enable TC1 interrupt service ; To clear TC1 interrupt request ; To enable TC1 timer Example: Setup the TC1M and TC1C with auto-reload function. (TC1_Counter=8-bit, TC1X8=0) B0BCLR B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC1X8 FTC1IEN FTC1ENB A,#20H TC1M,A A,#74H TC1C,A TC1R,A FTC1IEN FTC1IRQ FTC1ENB ALOAD1 ; To select TC1=Fcpu/2 as clock source ; To disable TC1 interrupt service ; To disable TC1 timer ; ; To set TC1 clock = Fcpu / 64 ; To set TC1C initial value = 74H ; (To set TC1 interval = 10 ms) ; To set TC1R auto-reload register ; To enable TC1 interrupt service ; To clear TC1 interrupt request ; To enable TC1 timer ; To enable TC1 auto-reload function. SONiX TECHNOLOGY CO., LTD Page 72 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Example: TC1 interrupt service routine without auto-reload function. (TC1_Counter=8-bit, TC1X8=0) ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; Store ACC value. 8 INT_SERVICE ; Interrupt vector B0BTS1 JMP B0BCLR MOV B0MOV . . JMP . . EXIT_INT: B0MOV B0MOV B0XCH RETI FTC1IRQ EXIT_INT FTC1IRQ A,#74H TC1C,A . . EXIT_INT . . A, PFLAGBUF PFLAG, A A, ACCBUF ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reload TC1C ; TC1 interrupt service routine ; End of TC1 interrupt service routine and exit interrupt vector ; Restore ACC value. ; Exit interrupt vector Example: TC1 interrupt service routine with auto-reload. (TC1_Counter=8-bit, TC1X8=0) ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; Store ACC value. 8 INT_SERVICE ; Interrupt vector B0BTS1 JMP B0BCLR . . JMP . . EXIT_INT: B0MOV B0MOV B0XCH RETI FTC1IRQ EXIT_INT FTC1IRQ . . EXIT_INT . . A, PFLAGBUF PFLAG, A A, ACCBUF ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; TC1 interrupt service routine ; End of TC1 interrupt service routine and exit interrupt vector ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 73 Revision 0.5 Preliminary TC1 CLOCK FREQUENCY OUTPUT (BUZZER) SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC1 timer counter provides a frequency output function. By setting the TC1 clock frequency, the clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1 output signal divides by 2. The TC1 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency. Figure 8-4The TC1OUT Pulse Frequency Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The TC1OUT frequency is 1KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 2KHz. The TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110, TC1C = TC1R = 131, TC1_Counter=8-bit, TC1X8=0 B0BCLR MOV B0MOV MOV B0MOV B0MOV B0BSET B0BSET B0BSET FTC1X8 A,#01100000B TC1M,A A,#131 TC1C,A TC1R,A FTC1OUT FALOAD1 FTC1ENB ; Set TC1X8 to 0 ; Set the TC1 rate to Fcpu/4 ; Set the auto-reload reference value ; Enable TC1 output to P5.3 and disable P5.3 I/O function ; Enable TC1 auto-reload function ; Enable TC1 timer SONiX TECHNOLOGY CO., LTD Page 74 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC PWM FUNCTION DESCRIPTION OVERVIEW PWM function is generated by TC0/TC1 timer counter and output the PWM signal to PWM0OUT pin (P5.4)/ PWM1OUT pin (P5.3). When code option TC0/TC1_Counter= 8-bit, the counter counts modulus 256, from 0-255, inclusive. The value of the 8-bit counter is compared to the contents of the reference register (TC0R/TC1R). When the reference register value (TC0R/TC1R) is equal to the counter value (TC0C/TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. Following table listed the low-to-high ratio (duty) of the PWM0/PWM1 output. For example, TC0_Counter=8-bit, all PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value (TC0C/TC1C) changes from FFH back to 00H, the PWM output is forced to high level. The pulse width ratio (duty cycle) is defined by the contents of the reference register (TC0R/TC1R) and is programmed in increments of 1:256. The 8-bit PWM data register TC0R/TC1R is write-only register. Different code option of TC0_Counter/TC1_Counter will cause different PWM Duty, so user can generate different PWM output by selection different TC0_Counter/TC1_Counter. PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to change the PWM's duty cycle is to modify the TC0R/TC1R. TC0X8/TC1X8 0 PWM0 Frequency Fosc/(2 10-TC0RATE PWM1 Frequency Fosc/(210-TC1RATE)/N )/N Fosc/(27-TC0RATE) /N Fosc/(27-TC1RATE) /N 1 The value of N depend on code option TC0_Counter/TC1_Counter TC0_Counter/TC1_Counter 8-bit 6-bit 5-bit 4-bit N 256 64 32 16 PWM Duty Cycle 0/256 ~ 255/256 0/64 ~ 63/64 0/32 ~ 31/32 0/16 ~ 15/16 Table 8-6. The PWM Frequency Calculation Formula TC0X8 TC1X8 0 0 0 0 1 1 1 1 TC0_Counter TC1_Counter 8-bit 6-bit 5-bit 4-bit 8-bit 6-bit 5-bit 4-bit TC0 Overflow boundary TC1 Overflow boundary FFh to 00h 3Fh to 40h 1Fh to 20h 0Fh to 10h FFh to 00h 3Fh to 40h 1Fh to 20h 0Fh to 10h PWM Duty Cycle 0/256 ~ 255/256 0/64 ~ 63/64 0/32 ~ 31/32 0/16 ~ 15/16 0/256 ~ 255/256 0/64 ~ 63/64 0/32 ~ 31/32 0/16 ~ 15/16 Max PWM Frequency (Fosc = 4MHz) 1.953125K 7.8125K 15.625K 31.25K 15.625 62.5K 125K 250K Note Overflow per 256 count Overflow per 64 count Overflow per 32 count Overflow per 16 count Overflow per 256 count Overflow per 64 count Overflow per 32 count Overflow per 16 count Table 8-7. The Maximum PWM Frequency Example (TC0RATE/TC1RATE = 111) SONiX TECHNOLOGY CO., LTD Page 75 Revision 0.5 Preliminary Reference Register Value (TC0R/TC1R) 0000 0000 0000 0001 0000 0010 ... SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC TC0/1_Counter=8-bit TC0/1_Counter=6-bit TC0/1_Counter=5-bit TC0/1_Counter=4-bit Duty Cycle Duty Cycle Duty Cycle Duty Cycle 0/256 0/64 0/32 0/16 1/256 1/64 1/32 1/16 2/256 2/64 2/32 2/16 ... ... ... ... 0000 1110 0000 1111 0001 0000 ... 14/256 15/256 16/256. ... 14/64 15/64 16/64 ... 14/32 15/32 16/32 ... 0001 1110 0001 1111 0010 0000 ... 30/256 31/256 32/256. ... 30/64 31/64 32/64 ... 0011 1110 0011 1111 0100 0000 ... 62/256 63/256 64/256. ... 1111 1110 1111 1111 254/256 255/256 62/64 63/64 N/A N/A N/A N/A 30/32 31/32 N/A N/A N/A N/A N/A N/A N/A N/A 14/16 15/16 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Table 8-8. The PWM Duty Cycle Table Note: Functionality is not guaranteed in shaded area. SONiX TECHNOLOGY CO., LTD Page 76 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 0 TC0/TC1 Clock 1 ..... 128 ..... 254 255 0 1 ..... 128 ..... 254 255 TC0R/TC1R = 00H High Low TC0R/TC1R = 01H High Low TC0R/TC1R = 80H High Low TC0R/TC1R = FFH Low Figure 8-5 The Output of PWM with different TC0R/TC1R. (TC0/TC1_Counter=8-bit) 0 1 2 ... 16 17 18 ... 32 33 34 ... 64 65 66 ... 255 0 1 ... TC0 Clock TC0R = 01H TC0_count:4-bit High Low High TC0R = 01H TC0_count:5-bit Low High TC0R = 01H TC0_count:6-bit Low TC0R = 01H TC0_count:8-bit High Low Figure 8-6 The Output of PWM with different TC0_Counter SONiX TECHNOLOGY CO., LTD Page 77 Revision 0.5 Preliminary PWM PROGRAM DESCRIPTION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The external high-speed oscillator clock is 4MHz. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110, TC0C = TC0R = 30, TC0X8 =0, TC0_Counter=8-bit B0BCLR MOV B0MOV MOV B0MOV MOV B0MOV B0BCLR B0BSET B0BSET FTC0X8 A,#01100000B TC0M,A A,#0x00 TC0C,A A,#30 TC0R,A FTC0OUT FPWM0OUT FTC0ENB ; Disable TC0OUT function. ; Enable PWM0 output to P5.4 and disable P5.4 I/O function ; Enable TC0 timer ; Set the TC0 rate to Fcpu/4 ;First Time Initial TC0 ; Set the PWM duty to 30/256 Note1: The TC0R and TC1R are write-only registers. Don't process them using INCMS, DECMS instructions. Note2: Set TC0C at initial is to make first duty-cycle correct. After TC0 is enabled, don't modify TC0R value to avoid duty cycle error of PWM output. Example: Modify TC0R/TC1R registers' value. MOV B0MOV INCMS B0MOV B0MOV A, #30H TC0R, A BUF0 A, BUF0 TC0R, A ; Input a number using B0MOV instruction. ; Get the new TC0R value from the BUF0 buffer defined by ; programming. Note2: That is better to set the TC0C and TC0R value together when PWM0 duty modified. It protects the PWM0 signal no glitch as PWM0 duty changing. That is better to set the TC1C and TC1R value together when PWM1 duty modified. It protects the PWM1 signal no glitch as PWM1 duty changing. Note3: The TC0OUT function must be set "0" when PWM0 output enable. The TC1OUT function must be set "0" when PWM1 output enable. Note4: The PWM can work with interrupt request. SONiX TECHNOLOGY CO., LTD Page 78 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 9 INTERRUPT OVERVIEW The SN8P1702A/SN8P1703A provides 3 interrupt sources, including two internal interrupts (TC0, TC1) and one external interrupts (INT0 ). The external interrupt can wakeup the chip from power down mode to high-speed normal mode. The external clock input pins of INT0 are shared with P0.0 pins. Once interrupt service is executed, the GIE bit in STKP register will clear to "0" for stopping other interrupt request. When interrupt service exits, the GIE bit will set to "1" to accept the next interrupts' request. All of the interrupt request signals are stored in INTRQ register. The user can program the chip to check INTRQ's content for setting executive priority. INTEN Interrupt enable reg ister TC0 time out TC1 time out INT0 trigger INTRQ 3-bit Latchs TC0IRQ TC1IRQ P00IRQ Interrupt enable gating Interrupt vector address (0008H) Global interrupt request signal Figure 9-1. The 7 Interrupts Note: The GIE bit must enable and all interrupt operations work. SONiX TECHNOLOGY CO., LTD Page 79 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC INTEN INTERRUPT ENABLE REGISTER INTEN is the interrupt request control register including two internal interrupts, one external interrupts enable control bits. One of the register to be set "1" is to enable the interrupt request function. Once of the interrupt occur, the program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed. INTEN initial value = x000 0000 0C9H Bit 7 Bit 6 0 TC1IEN INTEN R/W Bit0 Bit 5 TC0IEN R/W Bit 4 0 - Bit 3 0 - Bit 2 0 - Bit 1 0 - Bit 0 P00IEN R/W Bit5 Bit6 P00IEN:External P0.0 interrupt control bit. 0 = disable, 1 = enable. TC0IEN:Timer interrupt control bit. 0 = disable, 1 = enable. TC1IEN:Timer interrupt control bit. 0 = disable, 1 = enable. INTRQ INTERRUPT REQUEST REGISTER INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of these interrupt request occurs, the bit of the INTRQ register would be set "1". The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. INTRQ initial value = x000 0000 0C8H INTRQ Bit 7 0 Bit 6 TC1IRQ R/W Bit 5 TC0IRQ R/W Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 P00IRQ R/W Bit0 Bit5 Bit6 P00IRQ:External P0.0 interrupt request bit. 0 = non-request 1 = request. TC0IRQ:TC0 timer interrupt request controls bit. 0 = non request 1 = request. TC1IRQ:TC1 timer interrupt request controls bit. 0 = non request 1 = request. When interrupt occurs, the related request bit of INTRQ register will be set to "1" no matter the related enable bit of INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won't execute interrupt vector even when the related bit of INTRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. SONiX TECHNOLOGY CO., LTD Page 80 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC INTERRUPT OPERATION DESCRIPTION SN8P1702A/SN8P1703A provides 3 interrupts. The operation of the 3 interrupts is as following. GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level. STKP initial value = 0xxx 1111 0DFH STKP Bit 7 GIE R/W Bit 6 Bit 5 Bit 4 Bit 3 STKPB3 R/W Bit 2 STKPB2 R/W Bit 1 STKPB1 R/W Bit 0 STKPB0 R/W Bit7 GIE:Global interrupt control bit. 0 = disable 1 = enable. Example: Set global interrupt control bit (GIE). B0BSET FGIE ; Enable GIE Note: The GIE bit must enable and all interrupt operations work. SONiX TECHNOLOGY CO., LTD Page 81 Revision 0.5 Preliminary INT0 (P0.0) INTERRUPT OPERATION The P0.0 interrupt trigger direction is control by PEDGE register. PEDGE initial value = 0xx0 0xxx 0BFH PEDGE Bit 7 PEDGEN R/W Bit 6 Bit 5 Bit 4 P00G1 R/W Bit 3 P00G0 R/W SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Bit 2 - Bit 1 - Bit 0 - Bit7 PEDGEN: Interrupt and wakeup trigger edge control bit. 0 = Disable edge trigger function. Port 0: Low-level wakeup trigger and falling edge interrupt trigger. Port 1: Low-level wakeup trigger. 1 = Enable edge trigger function. P0.0: Wakeup and interrupt trigger is controlled by P00G1 and P00G0 bits. Port 1: Level change (falling or rising edge) wakeup trigger. P00G[1:0]: Port 0.0 edge select bits. 00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction. Bit[4:3] Example: INT0 interrupt request setup. B0BSET B0BCLR B0BSET FP00IEN FP00IRQ FGIE ; Enable INT0 interrupt service ; Clear INT0 interrupt request flag ; Enable GIE Example: INT0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV B0BTS1 JMP B0BCLR . . EXIT_INT: B0MOV B0MOV B0XCH RETI A, PFLAGBUF PFLAG, A A, ACCBUF A, ACCBUF A, PFLAG PFLAGBUF, A FP00IRQ EXIT_INT FP00IRQ . . ; Store ACC value. 8 INT_SERVICE ; Interrupt vector ; Check P00IRQ ; P00IRQ = 0, exit interrupt vector ; Reset P00IRQ ; INT0 interrupt service routine ; Restore ACC value. ; Exit interrupt vector When the INT0 trigger occurs, the P00IRQ will be set to "1" no matter the P00IEN is enable or disable. If the P00IEN = 1 and the trigger event P00IRQ is also set to be "1". As the result, the system will execute the interrupt vector (ORG 8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be "1". Moreover, the system won't execute interrupt vector even when the P00IRQ is set to be "1". Users need to be cautious with the operation under multi-interrupt situation. SONiX TECHNOLOGY CO., LTD Page 82 Revision 0.5 Preliminary TC0 INTERRUPT OPERATION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC When the TC0C counter occurs overflow, the TC0IRQ will be set to "1" however the TC0IEN is enable or disable. If the TC0IEN = 1, the trigger event will make the TC0IRQ to be "1" and the system enter interrupt vector. If the TC0IEN = 0, the trigger event will make the TC0IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: TC0 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC0IEN FTC0ENB A, #20H TC0M, A A, #74H TC0C, A FTC0IEN FTC0IRQ FTC0ENB FGIE ; Disable TC0 interrupt service ; Disable TC0 timer ; ; Set TC0 clock = Fcpu / 64 ; Set TC0C initial value = 74H ; Set TC0 interval = 10 ms ; Enable TC0 interrupt service ; Clear TC0 interrupt request flag ; Enable TC0 timer ; Enable GIE Example: TC0 interrupt service routine. ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; Store ACC value. 8 INT_SERVICE ; Interrupt vector B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: B0MOV B0MOV B0XCH FTC0IRQ EXIT_INT FTC0IRQ A, #74H TC0C, A . . A, PFLAGBUF PFLAG, A A, ACCBUF ; Check TC0IRQ ; TC0IRQ = 0, exit interrupt vector ; Reset TC0IRQ ; Reset TC0C. ; TC0 interrupt service routine ; Restore ACC value. RETI ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 83 Revision 0.5 Preliminary TC1 INTERRUPT OPERATION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC When the TC1C counter occurs overflow, the TC1IRQ will be set to "1" however the TC1IEN is enable or disable. If the TC1IEN = 1, the trigger event will make the TC1IRQ to be "1" and the system enter interrupt vector. If the TC1IEN = 0, the trigger event will make the TC1IRQ to be "1" but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation. Example: TC1 interrupt request setup. B0BCLR B0BCLR MOV B0MOV MOV B0MOV B0BSET B0BCLR B0BSET B0BSET FTC1IEN FT C1ENB A, #20H TC1M, A A, #74H TC1C, A FTC1IEN FTC1IRQ FTC1ENB FGIE ; Disable TC1 interrupt service ; Disable TC1 timer ; ; Set TC1 clock = Fcpu / 64 ; Set TC1C initial value = 74H ; Set TC1 interval = 10 ms ; Enable TC1 interrupt service ; Clear TC1 interrupt request flag ; Enable TC1 timer ; Enable GIE Example: TC1 interrupt service routine. ORG JMP INT_SERVICE: B0XCH B0MOV B0MOV A, ACCBUF A, PFLAG PFLAGBUF, A ; Store ACC value. 8 INT_SERVICE ; Interrupt vector ; B0BTS1 JMP B0BCLR MOV B0MOV . . EXIT_INT: B0MOV B0MOV B0XCH A, PFLAGBUF PFLAG, A A, ACCBUF FTC1IRQ EXIT_INT FTC1IRQ A, #74H TC1C, A . . ; Check TC1IRQ ; TC1IRQ = 0, exit interrupt vector ; Reset TC1IRQ ; Reset TC1C. ; TC1 interrupt service routine ; Restore ACC value. RETI ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 84 Revision 0.5 Preliminary MULTI-INTERRUPT OPERATION SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC In most conditions, the software designer uses more than one interrupt request. Processing multi-interrupt request needs to set the priority of these interrupt requests. The IRQ flags of the 7 interrupt are controlled by the interrupt event occurring. But the IRQ flag set doesn't mean the system to execute the interrupt vector. The IRQ flags can be triggered by the events without interrupt enable. Just only any the event occurs and the IRQ will be logic "1". The IRQ and its trigger event relationship is as the below table. Interrupt Name P00IRQ TC0IRQ TC1IRQ Trigger Event Description P0.0 trigger. Falling/Rising/Both. TC0C overflow. TC1C overflow. There are two things need to do for multi-interrupt. One is to make a good priority for these interrupt requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following. SONiX TECHNOLOGY CO., LTD Page 85 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC Example: How does users check the interrupt request in multi-interrupt situation? ORG B0XCH B0MOV B0MOV INTP00CHK: B0BTS1 JMP B0BTS0 JMP INTTC0CHK: B0BTS1 JMP B0BTS0 JMP INTTC1HK: B0BTS1 JMP B0BTS0 JMP INT_EXIT: B0MOV B0MOV B0XCH RETI A, PFLAGBUF PFLAG, A A, ACCBUF FTC1IEN INT_EXIT FTC1IRQ INTTC1 FTC0IEN INTTC1CHK FTC0IRQ INTTC0 FP00IEN INTTC0CHK FP00IRQ INTP00 8 A, ACCBUF A, PFLAG PFLAGBUF, A ; Interrupt vector ; Store ACC value. ; ; Check INT0 interrupt request ; Check P00IEN ; Jump check to next interrupt ; Check P00IRQ ; Jump to INT0 interrupt service routine ; Check TC0 interrupt request ; Check TC0IEN ; Jump check to next interrupt ; Check TC0IRQ ; Jump to TC0 interrupt service routine ; Check TC1 interrupt request ; Check TC1IEN ; Jump check to next interrupt ; Check TC1IRQ ; Jump to TC1 interrupt service routine ; Restore ACC value. ; Exit interrupt vector SONiX TECHNOLOGY CO., LTD Page 86 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 10 I/O PORT OVERVIEW The SN8P1702A/SN8P1703A provides up to 4 ports for users' application, consisting of one input only port (P0), four I/O ports (P1, P4, P5). The direction of I/O port is selected by PnM register and PnUR register (N=0,1,4,5) is defined for user setting pull-up register. After the system resets, all ports work as input function without pull-up resistors. Port1, 4, 5 structure Port0 structure PUR PUR PnM PnM Pin Pin Int. bus PnM Latch Int. bus Figure 10-1. The I/O Port Block Diagram Note : All of the latch output circuits are push-pull structures. SONiX TECHNOLOGY CO., LTD Page 87 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC I/O PORT FUNCTION TABLE Port/Pin P0.0 P1.0~P1.1 P4.0~P4.3 P5.0~P5.5 I/O I I/O I/O I/O Function Description General-purpose input function External interrupt (INT0) Wakeup for power down mode General-purpose input/output function Wakeup for power down mode General-purpose input/output function ADC analog signal input General-purpose input/output function Table 10-1. I/O Function Table Remark SONiX TECHNOLOGY CO., LTD Page 88 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC PULL-UP RESISTERS SN8P1702A/SN8P1703A series chips built-in pull-up resisters in port 0, port 1, port4 and port 5. User can set pull-up register by pin Register Name Address Bit Bit's Name Read/Write After reset Register Name Address Bit Bit's Name Read/Write After reset Register Name Address Bit Bit's Name Read/Write After reset Register Name Address Bit Bit's Name Read/Write After reset P0UR E0H Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 P1UR E1H Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 P4UR E4H Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 P5UR 0E0H Bit 7 0 Bit 6 0 Bit 5 P55R R/W 0 Bit 4 P54R R/W 0 Bit 3 P53R R/W 0 Bit 2 P52R R/W 0 Bit 1 P51R R/W 0 Bit 0 P50R R/W 0 Bit 3 P43R R/W 0 Bit 2 P42R R/W 0 Bit 1 P41R R/W 0 Bit 0 P40R R/W 0 Bit 3 0 Bit 2 0 Bit 1 P11R R/W 0 Bit 0 P10R R/W 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 P00R R/W 0 CHIP SN8P1703A ORG 0x10 Main: MOV B0MOV A, #01H P0UR,A ; Enable port 0.0 pull-up resisters Example 2: Enable all pull-up resisters CHIP SN8P1703A ORG 0x10 Main: MOV A, #01H B0MOV P0UR,A ; Enable port 0 pull-up resisters MOV A, #03H B0MOV P1UR,A ; Enable port 1 pull-up resisters MOV A, #0FH B0MOV P4UR,A ; Enable port 4 pull-up resisters MOV A, #01FH B0MOV P5UR,A ; Enable port 5 pull-up resisters Note: Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup in sleep mode. SONiX TECHNOLOGY CO., LTD Page 89 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC I/O PORT MODE The port direction is programmed by PnM register. Port 0 is always input mode. Port 1,2,4 and 5 can select input or output direction. P1M initial value = xxxx xx00 0C1H P1M Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 P11M R/W Bit 0 P10M R/W Bit[1:0] P1[1:0]M:P1.0~P1.1 I/O direction control bit. 0 = input mode 1 = output mode. P4M initial value = xxxx 0000 0C4H P4M Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 P43M R/W Bit 2 P42M R/W Bit 1 P41M R/W Bit 0 P40M R/W Bit[3:0] P4[3:0]M:P4.0~P4.3 I/O direction control bit. 0 = input mode 1 = output mode. P5M initial value = xx00 0000 0C5H P5M Bit 7 0 Bit 6 0 Bit 5 P55M R/W Bit 4 P54M R/W Bit 3 P53M R/W Bit 2 P52M R/W Bit 1 P51M R/W Bit 0 P50M R/W Bit[5:0] P5[5:0]M: P5.0~P5.5 I/O direction control bit. 0 = input mode 1 = output mode. The each bit of PnM is set to "0", the I/O pin is input mode. The each bit of PnM is set to "1", the I/O pin is output mode. Input mode is with pull-up resistor controlled by setting @SET_UP macro. The output mode disables the pull-up resistors no matter pull-up resistors is set or not. The PnM registers are read/write bi-direction registers. Users can program them by bit control instructions (B0BSET, B0BCLR). SONiX TECHNOLOGY CO., LTD Page 90 Revision 0.5 Preliminary Example: I/O mode selecting. CLR CLR CLR P1M P4M P5M SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ; Set all ports to be input mode. MOV B0MOV B0MOV B0MOV A, #0FFH P1M, A P4M, A P5M, A ; Set all ports to be output mode. B0BCLR B0BSET P1M.0 P1M.0 ; Set P1.0 to be input mode. ; Set P1.0 to be output mode. SONiX TECHNOLOGY CO., LTD Page 91 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC I/O PORT DATA REGISTER P0 initial value = xxxx x000 0D0H P0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P00 R P1 initial value = xx00 0000 0D1H P1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 P11 R/W Bit 0 P10 R/W P4 initial value = 0000 0000 0D4H P4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 P43 R/W Bit 2 P42 R/W Bit 1 P41 R/W Bit 0 P40 R/W P5 initial value = 0000 0000 0D5H P5 Bit 7 Bit 6 Bit 5 P55 R/W Bit 4 P54 R/W Bit 3 P53 R/W Bit 2 P52 R/W Bit 1 P51 R/W Bit 0 P50 R/W Example: Read data from input port. B0MOV B0MOV B0MOV B0MOV A, P0 A, P1 A, P4 A, P5 ; Read data from Port 0 ; Read data from Port 1 ; Read data from Port 4 ; Read data from Port 5 Example: Write data to output port. MOV B0MOV B0MOV B0MOV A, #55H P1, A P4, A P5, A ; Write data 55H to Port 1, Port 4, Port 5 SONiX TECHNOLOGY CO., LTD Page 92 Revision 0.5 Preliminary Example: Write one bit data to output port. B0BSET B0BSET B0BCLR B0BCLR P1.1 P4.0 P1.0 P5.5 SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ; Set P1.1 and P4.0 to be "1". ; Set P1.0 and P5.5 to be "0". Example: Port bit test. B0BTS1 . B0BTS0 P0.0 P1.1 ; Bit test 1 for P0.0 ; Bit test 0 for P1.1 SONiX TECHNOLOGY CO., LTD Page 93 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 11 4-CHANNEL ANALOG TO DIGITAL CONVERTER OVERVIEW This analog to digital converter of SN8P1702A/SN8P1703A has 4-input sources with up to 4096-step resolution to transfer analog signal into 12-bits digital data. The sequence of ADC operation is to select input source (AIN0 ~ AIN3) at first, then set GCHS and ADS bit to "1" to start conversion. When the conversion is complete, the ADC circuit will set EOC bit to "1" and final value output in ADB register. This ADC circuit can select between 8-bit and 12-bit resolution operation by programming ADLEN bit in ADR register. AIN0/P4.0 DA BUS TA AIN1/P4.1 AIN2/P4.2 AIN3/P4.3 A/D CONVERTER 8/12 (ADC) Figure 11-1. AD Converter Function Diagram Note: For 8-bit resolution, the conversion time is 12 steps. For 12-bit resolution, the conversion time is 16 steps. Note: The analog input level must be between the AVREFH and VSS. Note: The AVREFH level must be between the VDD and VSS+1.2V. SONiX TECHNOLOGY CO., LTD Page 94 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ADM REGISTER ADM initial value = 0000 x000 0B1H ADM Bit 7 ADENB R/W Bit 6 ADS R/W Bit 5 EOC R/W Bit 4 GCHS R/W Bit 3 Bit 2 Bit 1 CHS1 R/W Bit 0 CHS0 R/W Bit[1:0] Bit4 Bit5 Bit6 Bit7 CHS[1:0]: ADC input channels select bit. 00 = AIN0 01 = AIN1 10 = AIN2 11 = AIN3 GCHS:Global channel select bit. 0 = to disable AIN channel 1 = to enable AIN channel. EOC: ADC status bit. 0 = Progressing 1 = End of converting and reset ADENB bit. ADS:ADC start bit. 0 = stop 1 = starting. ADENB:ADC control bit. 0 = disable 1 = enable. ADR REGISTERS ADR initial value = x00x 0000 0B3H ADR Bit 7 Bit 6 ADCKS1 R/W Bit 5 ADLEN R/W Bit 4 ADCKS0 R/W Bit 3 ADB3 R Bit 2 ADB2 R Bit 1 ADB1 R Bit 0 ADB0 R Bit[3:0] Bit5 Bit6,Bit4 ADBn: ADC data buffer. ADB11~ADB4 data for 8-bit ADC. ADB11~ADB0 data for 12-bit ADC. ADLEN: ADC's resolution select bits. 0 = 8-bit 1 = 12-bit. ADCKS1, ADCKS0: ADC's clock source select bit. ADCKS1 ADCKS0 ADC Clock Source Note 0 0 Fcpu/4 Both validate in Normal mode and Slow mode 0 1 Fcpu/2 Both validate in Normal mode and Slow mode 1 0 Fhosc Only validate in Normal mode 1 1 Fhosc/2 Only validate in Normal mode SONiX TECHNOLOGY CO., LTD Page 95 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ADB REGISTERS ADB initial value = xxxx xxxx 0B2H ADB Bit 7 ADB11 R Bit 6 ADB10 R Bit 5 ADB9 R Bit 4 ADB8 R Bit 3 ADB7 R Bit 2 ADB6 R Bit 1 ADB5 R Bit 0 ADB4 R ADB is ADC data buffer to store AD converter result. The ADB is only 8-bit register including bit4~bit11 ADC data. To combine ADB register and the low-nibble of ADR will get full 12-bit ADC data buffer. The ADC buffer is a read-only register. In 8-bit ADC mode, the ADC data is stored in ADB register. In 12-bit ADC mode, the ADC data is stored in ADB and ADR registers. Note: ADB[0:11] value is unknown when power on. SONiX TECHNOLOGY CO., LTD Page 96 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC P4CON REGISTERS ADB initial value = xxxx 0000 0AEH P4CON Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 P4CON3 R/W Bit 2 P4CON2 R/W Bit 1 P4CON1 R/W Bit 0 P4CON0 R/W P4CON is Port4 Configuration register. This register can avoid current leakage in unselected ADC channel, which connected to an analog input source. P4CON [3:0] sets to high will isolate related Port4 digital input path outside chip. For example, both AIN0 (Port4.0) and AIN1 (Port4.1) are connected to analog input signal, and AIN0 be selected as conversion channel (CHS [1:0] = 00), this mean the unselected channel P4.1 maybe in digital input mode (if P41M = 0) In this condition will possible leak current from analog input source. Set P4CON1 = "1" can block P4.1 digital input path to avoid the current leakage from AIN1. For the same reason, P4CON0 must set to "1" when conversion channel is AIN1. So any Port4 pin be connected to analog input source should be set related bit of P4CON as high to avoid unpredictable current leakage. Especially before entering Sleep mode, remember to set related bit of P4CON as "1". Bit [3:0] P4CON: Port4 Configuration register. 0 Pass P4.3 digital path into chip. P4CON3 1 Isolate P4.3 digital path into chip 0 Pass P4.2 digital path into chip. P4CON2 1 Isolate P4.2 digital path into chip 0 Pass P4.1 digital path into chip. P4CON1 1 Isolate P4.1 digital path into chip 0 Pass P4.0 digital path into chip. P4CON0 1 Isolate P4.0 digital path into chip Note 1: When Port4 is general I/O port, set related P4CON [3:0] = "0" Note 2: When Port4 is ADC input channel, set related P4CON [3:0] = "1" The AIN's input voltage vs. ADB's output data AIN n ADB11 ADB10 ADB9 0/4096*AVREFH 0 0 0 1/4096*AVREFH 0 0 0 . . . . . . . . . . . . 4094/4096*AVREFH 1 1 1 4095/4096*AVREFH 1 1 1 ADB8 0 0 . . . 1 1 ADB7 0 0 . . . 1 1 ADB6 0 0 . . . 1 1 ADB5 0 0 . . . 1 1 ADB4 0 0 . . . 1 1 ADB3 0 0 . . . 1 1 ADB2 0 0 . . . 1 1 ADB1 0 0 . . . 1 1 ADB0 0 1 . . . 0 1 For different applications, users maybe need more than 8-bit resolution but less than 12-bit ADC converter. To process the ADB and ADR data can make the job well. First, the AD resolution must be set 12-bit mode and then to execute ADC converter routine. Then delete the LSB of ADC data and get the new resolution result. The table is as following. ADC ADB11 Resolution 8-bit O 9-bit O 10-bit O 11-bit O 12-bit O O = Selected, x = Delete ADB ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 ADB3 ADR ADB2 ADB1 ADB0 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O x O O O O x x O O O x x x O O x x x x O SONiX TECHNOLOGY CO., LTD Page 97 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ADC CONVERTING TIME 12-bit ADC conversion time = 1/(ADC clock /4)*16 sec 8-bit ADC conversion time = 1/(ADC clock /4)*12 sec High clock (Fosc) is @3.58MHz ADLEN ADCKS1 ADCKS0 0 0 0 1 0 (8-bit) 1 0 1 1 0 0 0 1 1 (12-bit) 1 0 1 1 ADC Clock Fcpu/4 Fcpu/2 Fhosc Fhosc/2 Fcpu/4 Fcpu/2 Fhosc Fhosc/2 ADC conversion time 1/((3.58MHz/4)/4/4)*12 = 214.5 us 1/((3.58MHz/4)/2/4)*12 = 107.3 us 1/(3.58MHz/4)*12 = 13.4 us 1/(3.58MHz/2/4)*12 = 26.8 us 1/((3.58MHz/4)/4/4)*16 = 286 us 1/((3.58MHz/4)/2/4)*16 = 143 us 1/(3.58MHz/4)*16 = 17.9 us 1/(3.58MHz/2/4)*16 = 35.8 us Example: To set AIN0 ~ AIN1 for ADC input and executing 12-bit ADC ADC0: MOV B0MOV B0SET B0CLR MOV B0MOV B0SET B0BSET WADC0: B0BTS1 JMP B0MOV ADC1: B0SET B0CLR MOV B0MOV B0BSET . QEXADC: B0BCLR FGCHS ; To release AINx input channel FP4CON0 FP4CON1 A,#91H ADM,A FADS . ;Isolate AIN0 signal to avoid current leakage ;Pass AIN1 signal into ADC ; ; To enable ADC and set AIN1 input ; To start conversion . FEOC WADC0 A,ADB ; To skip, if end of converting =1 ; else, jump to WADC0 ; To get AIN0 input data A, #60H ADR, A FP4CON1 FP4CON0 A,#90H ADM,A P4CON1 FADS ; To set 12-bit ADC and ADC clock = Fosc. ;Isolate AIN1 signal to avoid current leakage ;Pass AIN0 signal into ADC ; To enable ADC and set AIN0 input ; To enable ADC and set AIN0 input ; To start conversion SONiX TECHNOLOGY CO., LTD Page 98 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ADC CIRCUIT VDD AVREF Analog Signal Input 0.1uF AIN0/P40 MCU AVREFH is connected to VDD. VDD Reference Voltage Input Analog Signal Input 47uF 0.1uF AVREF AIN0/P40 MCU AVREFH is connected to external AD reference voltage. Figure 11-2. The AINx and AVREFH Circuit of AD Converter Note: The capacitor between AIN and GND is a bypass capacitor. It is helpful to stable the analog signal. Users can omit it. SONiX TECHNOLOGY CO., LTD Page 99 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 12 CODING ISSUE TEMPLATE CODE ;******************************************************************************* ; FILENAME : TEMPLATE.ASM ; AUTHOR : SONiX ; PURPOSE : Template Code for SN8X17XX ; REVISION : 09/01/2002 V1.0 First issue ;******************************************************************************* ;* (c) Copyright 2002, SONiX TECHNOLOGY CO., LTD. ;******************************************************************************* CHIP SN8P1703A ; Select the CHIP ;------------------------------------------------------------------------------; Include Files ;------------------------------------------------------------------------------.nolist ; do not list the macro file INCLUDESTD INCLUDESTD INCLUDESTD .list MACRO1.H MACRO2.H MACRO3.H ; Enable the listing function ;------------------------------------------------------------------------------; Constants Definition ;------------------------------------------------------------------------------; ONE EQU 1 ;------------------------------------------------------------------------------; Variables Definition ;------------------------------------------------------------------------------.DATA org DS DS DS DS org DS 0h 1 1 1 1 100h 20 ;Bank 0 data section start from RAM address 0x000 ;Temporary buffer for main loop ;Temporary buffer for ISR ;Accumulator buffer ;PFLAG buffer ;Bank 1 data section start from RAM address 0x100 ;Temporary buffer in bank 1 Wk00B0 Iwk00B0 AccBuf PflagBuf BufB1 ;------------------------------------------------------------------------------; Bit Flag Definition ;------------------------------------------------------------------------------Wk00B0_0 EQU Wk00B0.0 ;Bit 0 of Wk00B0 Iwk00B0_1 EQU Iwk00B0.1 ;Bit 1 of Iwk00 SONiX TECHNOLOGY CO., LTD Page 100 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ;------------------------------------------------------------------------------; Code section ;------------------------------------------------------------------------------.CODE ORG jmp ORG jmp 0 Reset 8 Isr ;Code section start ;Reset vector ;Address 4 to 7 are reserved ;Interrupt vector ORG 10h ;------------------------------------------------------------------------------; Program reset section ;------------------------------------------------------------------------------Reset: mov A,#07Fh ;Initial stack pointer and b0mov STKP,A ;disable global interrupt b0mov PFLAG,#00h ;pflag = x,x,x,x,x,c,dc,z b0mov RBANK,#00h ;Set initial RAM bank in bank 0 mov A,#40h ;Clear watchdog timer and initial system mode b0mov OSCM,A call call b0bset ClrRAM SysInit FGIE ;Clear RAM ;System initial ;Enable global interrupt ;------------------------------------------------------------------------------; Main routine ;------------------------------------------------------------------------------Main: b0bset FWDRST ;Clear watchdog timer call jmp MnApp Main ;------------------------------------------------------------------------------; Main application ;------------------------------------------------------------------------------MnApp: ; Put your main program here ret ;----------------------------------; Jump table routine ;----------------------------------ORG 0x0100 ;The jump table should start from the head ;of boundary. b0mov A,Wk00 and A,#3 ADD PCL,A jmp JmpSub0 jmp JmpSub1 jmp JmpSub2 ;----------------------------------- SONiX TECHNOLOGY CO., LTD Page 101 Revision 0.5 Preliminary JmpSub0: ; Subroutine 1 jmp JmpExit JmpSub1: ; Subroutine 2 jmp JmpExit JmpSub2: ; Subroutine 3 jmp JmpExit JmpExit: ret SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ;Return Main ;------------------------------------------------------------------------------; Isr (Interrupt Service Routine) ; Arguments : ; Returns : ; Reg Change: ;------------------------------------------------------------------------------Isr: ;----------------------------------; Save ACC and system registers ;----------------------------------b0xch A,AccBuf ;B0xch instruction do not change C,Z flag b0mov A,PFLAG b0mov PflagBuf,A ;----------------------------------; Check which interrupt happen ;----------------------------------IntP00Chk: b0bts1 FP00IEN jmp IntTc0Chk ;Modify this line for another interrupt b0bts0 FP00IRQ jmp P00isr ;If necessary, insert another interrupt checking here IntTc0Chk: b0bts1 jmp b0bts0 jmp FTC0IEN IsrExit FTC0IRQ TC0isr ;Suppose TC0 is the last interrupt which you ;want to check ;----------------------------------; Exit interrupt service routine ;----------------------------------IsrExit: ; Following two lines for SN8X1702 only b0mov A,PFLAG b0mov PflagBuf,A b0xch A,AccBuf ;B0xch instruction do not change C,Z flag reti ;Exit the interrupt routine SONiX TECHNOLOGY CO., LTD Page 102 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC ;------------------------------------------------------------------------------; INT0 interrupt service routine ;------------------------------------------------------------------------------P00isr: b0bclr FP00IRQ ;Process P0.0 external interrupt here jmp IsrExit ;------------------------------------------------------------------------------; TC0 interrupt service routine ;------------------------------------------------------------------------------TC0isr: b0bclr FTC0IRQ ;Process TC0 timer interrupt here jmp IsrExit ;------------------------------------------------------------------------------; SysInit ; Initialize I/O, Timer, Interrupt, etc. ;------------------------------------------------------------------------------SysInit: ret ;------------------------------------------------------------------------------; ClrRAM ; Use index @YZ to clear RAM (00h~7Fh) ;------------------------------------------------------------------------------ClrRAM: ; RAM Bank 0 clr b0mov ClrRAM10: clr decms jmp clr ; RAM Bank 1 mov b0mov b0mov ClrRAM20: clr decms jmp clr ret Y Z,#0x7f ;Select bank 0 ;Set @YZ address from 7fh @YZ Z ClrRAM10 @YZ ;Clear @YZ content ;z = z - 1 , skip next if z=0 ;Clear address 0x00 A,#1 Y,A Z,#0x7f ;Select bank 1 ;Set @YZ address from 17fh @YZ Z ClrRAM20 @YZ ;Clear @YZ content ;z = z - 1 , skip next if z=0 ;Clear address 0x100 ;------------------------------------------------------------------------------ENDP SONiX TECHNOLOGY CO., LTD Page 103 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC PROGRAM CHECK LIST Item Pull-up Resister detailed information. All bits those are marked as "0" (undefined bits) in system registers should be set "0" to avoid unpredicted system errors. Set ADC input pin I/O direction as input mode and disable pull-up resister of ADC input pin Set PWM0 (P5.4) pin as output mode. Set PWM1 (P5.3) pin as output mode. Do not enable interrupt before initializing RAM. Non-used I/O ports should be pull-up or pull-down in input mode, or be set as low in output mode to save current consumption. Enable on-chip pull-up resisters of port 0 and port 1 to avoid unpredicted wakeup. Be careful of function call and interrupt service routine operation. Don't let stack buffer overflow or underflow. 1. Write 0x7F into STKP register to initial stack pointer and disable global interrupt System Initial 2. Clear all RAM. 3. Initialize all system register even unused registers. 1. Enable OSG and High_Clk / 2 code option together 2. Enable the watchdog option and internal RC for the watchdog clock to protect system crash. Noisy Immunity 3. Non-used I/O ports should be set as output low mode or input with pull-up resistors. 4. Constantly refresh important system registers and variables in RAM to avoid system crash by a high electrical fast transient noise. Description Use PnUR register to enable or disable on-chip pull-up resisters. Refer I/O port chapter for Undefined Bits ADC PWM0 PWM1 Interrupt Non-Used I/O Sleep Mode Stack Buffer SONiX TECHNOLOGY CO., LTD Page 104 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 13 INSTRUCTION SET TABLE Field M O V E Mnemonic Description C - DC - Z Cycle 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 1+S 2 2 2 2 1 - MOV MOV B0MOV B0MOV MOV B0MOV XCH B0XCH MOVC ADC ADC ADD ADD B0ADD ADD SBC SBC SUB SUB SUB DAA AND AND AND OR OR OR XOR XOR XOR SWAP SWAPM RRC RRCM RLC RLCM CLR BCLR BSET B0BCLR B0BSET CMPRS CMPRS INCS INCMS DECS DECMS BTS0 BTS1 B0BTS0 B0BTS1 JMP CALL RET RETI NOP @SET_PUR A,M M,A A,M M,A A,I M,I A,M A,M A,M M,A A,M M,A M,A A,I A,M M,A A,M M,A A,I AM MA A M (bank 0) M (bank 0) A AI M I, (M = only for Working registers R, Y, Z , RBANK & PFLAG) A M A M (bank 0) R, A ROM [Y,Z] A A + M + C, if occur carry, then C=1, else C=0 M A + M + C, if occur carry, then C=1, else C=0 A A + M, if occur carry, then C=1, else C=0 M A + M, if occur carry, then C=1, else C=0 M (bank 0) M (bank 0) + A, if occur carry, then C=1, else C=0 A A + I, if occur carry, then C=1, else C=0 A A - M - /C, if occur borrow, then C=0, else C=1 M A - M - /C, if occur borrow, then C=0, else C=1 A A - M, if occur borrow, then C=0, else C=1 M A - M, if occur borrow, then C=0, else C=1 A A - I, if occur borrow, then C=0, else C=1 To adjust ACC's data format from HEX to DEC. A A and M M A and M A A and I A A or M M A or M A A or I A A xor M M A xor M A A xor I A (b3~b0, b7~b4) M(b7~b4, b3~b0) M(b3~b0, b7~b4) M(b7~b4, b3~b0) A RRC M M RRC M A RLC M M RLC M M0 M.b 0 M.b 1 M(bank 0).b 0 M(bank 0).b 1 ZF,C A - I, If A = I, then skip next instruction ZF,C A - M, If A = M, then skip next instruction A M + 1, If A = 0, then skip next instruction M M + 1, If M = 0, then skip next instruction A M - 1, If A = 0, then skip next instruction M M - 1, If M = 0, then skip next instruction If M.b = 0, then skip next instruction If M.b = 1, then skip next instruction If M(bank 0).b = 0, then skip next instruction If M(bank 0).b = 1, then skip next instruction PC15/14 RomPages1/0, PC13~PC0 d Stack PC15~PC0, PC15/14 RomPages1/0, PC13~PC0 d PC Stack PC Stack, and to enable global interrupt No operation Enable or disable pull-up resisters. Bit N of VAL: "0" disable port N pull-up, "1" enable port N pull-up A R I T H M E T I C L O G I C A,M M,A A,I A,M M,A A,I A,M M,A A,I M M M M M M M M.b M.b M.b M.b A,I A,M M M M M M.b M.b M.b M.b d d P R O C E S S B R A N C H M I S C VAL Table 13-1. Instruction Set Table Note 1: Any instruction that read/write from 0SCM, will add an extra cycle. SONiX TECHNOLOGY CO., LTD Page 105 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 14 ELECTRICAL CHARACTERISTIC ABSOLUTE MAXIMUM RATING (All of the voltages referenced to Vss) Supply voltage (Vdd)............................................................................................................... - 0.3V ~ 6.0V Input in voltage (Vin)..................................................................................................Vss - 0.2V ~ Vdd + 0.2V Operating ambient temperature (Topr)......................................................................................-20C ~ + 70C Storage ambient temperature (Tstore)....................................................................................-30C ~ + 125C Power consumption (Pc).................................................................................................................500 mW STANDARD ELECTRICAL CHARACTERISTIC (All of voltages referenced to Vss, Vdd = 5.0V, Fosc = 3.579545 MHz, ambient temperature is 25C unless otherwise note.) PARAMETER SYM. DESCRIPTION MIN. TYP. MAX. UNIT Normal mode, Vpp = Vdd 2.2 5.0 5.5 Operating voltage Vdd V Programming mode, Vpp = 12.5V 4.5 5.0 5.5 RAM Data Retention voltage Vdr 1.5 V Internal POR Vpor Vdd rise rate to ensure internal power-on reset 0.05 V/ms ViL1 All input pins except those specified below Vss 0.3Vdd V ViL2 Input with Schmitt trigger buffer - Port0 Vss 0.2Vdd V Input Low Voltage ViL3 Reset pin ; Xin ( in RC mode ) Vss 0.2Vdd V ViL4 Xin ( in X'tal mode ) Vss 0.3Vdd V ViH1 All input pins except those specified below 0.7Vdd Vdd V ViH2 Input with Schmitt trigger buffer -Port0 0.8Vdd Vdd V Input High Voltage ViH3 Reset pin ; Xin ( in RC mode ) 0.9Vdd Vdd V ViH4 Xin ( in X'tal mode ) 0.7Vdd Vdd V Reset pin leakage current Ilekg Vin = Vdd 2 uA I/O port pull-up resistor Rup Vin = Vss , Vdd = 5V 100 K I/O port input leakage current Ilekg Pull-up resistor disable, Vin = Vdd 2 uA Port1 output source current IoH Vop = Vdd - 0.5V 15 mA sink current IoL Vop = Vss + 0.5V 15 Port4 output source current IoH Vop = Vdd - 0.5V 15 mA sink current IoL Vop = Vss + 0.5V 15 Port5 output source current IoH Vop = Vdd - 0.5V 15 mA sink current IoL Vop = Vss + 0.5V 15 INTn trigger pulse width Tint0 INT0 interrupt request pulse width 2/fcpu cycle AVREFH input voltage AVref Vdd = 5.0V 1.2V Vdd V AIN0 ~ AIN3 input voltage Vani Vss+0.2 AVref V Crystal type or ceramic resonator 32768 4M 16M Oscillator Frequency Fhosc VDD = 3V, RC type for external mode Hz 6M VDD = 5V, RC type for external mode 10M Vdd= 5V 4Mhz 2.5 6 mA Run Mode Idd1 Vdd= 3V 4Mhz 1 2 mA (Low Power Disable) Vdd= 3V 32768Hz 40 80 uA Vdd= 5V 4Mhz 1.6 3 mA Run Mode Idd2 (Low Power Enable) Vdd= 3V 4Mhz 0.7 1.5 mA Supply Current Vdd= 5V 32KHz Int. RC 30 60 uA Slow mode (Disable ADC) Idd3 (Stop High Clock) Vdd= 3V 16KHz Int. RC 7 20 uA Vdd= 5V 1 2 uA Idd4 Sleep mode Vdd= 3V 0.6 uA Vdd= 5V 32KHz Int. RC 16 40 Green Mode Idd5 uA (Stop High Clock) Vdd= 3V 16KHz Int. RC 3 10 ADC current consumption IADC Vdd=5.0V Vdd=3.0V 0.6 0.4 1 0.8 mA mA LVD Detect Voltage Vdet Low voltage detect level - 1.8 - V SONiX TECHNOLOGY CO., LTD Page 106 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC 15 PACKAGE INFORMATION P-DIP18 PIN Symbols A A1 A2 D E E1 L B MIN. 0.015 0.125 0.880 0.245 0.115 0.335 0 NOR. 0.130 0.900 0.300BSC. 0.250 0.130 0.355 7 MAX. 0.210 0.135 0.920 0.255 0.150 0.375 15 UNIT : INCH SONiX TECHNOLOGY CO., LTD Page 107 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SOP18 PIN Symbols A A1 D E H L MIN. 0.093 0.004 0.447 0.291 0.394 0.016 0 MAX. 0.104 0.012 0.463 0.299 0.419 0.050 8 UNIT : INCH SONiX TECHNOLOGY CO., LTD Page 108 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC P-DIP 20 PIN SONiX TECHNOLOGY CO., LTD Page 109 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SOP 20 PIN SONiX TECHNOLOGY CO., LTD Page 110 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SSOP20 PIN Symbols A A1 A2 b b1 C C1 D E E1 e h L L1 ZD Y MIN, 1.35 0.10 0.20 0.20 0.18 0.18 8.56 5.80 3.80 0.25 0.40 1.00 0 DIMENSION (MM) NOM. 1.60 0.15 0.254 0.254 0.203 0.203 8.66 6.00 3.90 0.635 BSC 0.42 0.635 1.05 1.50 REF - MAX. 1.75 0.25 1.50 0.30 0.28 0.25 0.23 8.74 6.20 4.00 0.50 1.27 1.10 0.10 8 MIN. 53 4 8 8 7 7 337 228 150 10 16 39 0 DIMENSION (MIL) NOM. 63 6 10 11 8 8 341 236 154 25 BSC 17 25 41 58 REF - MAX. 69 10 59 12 11 10 9 344 244 157 20 50 43 4 8 SONiX TECHNOLOGY CO., LTD Page 111 Revision 0.5 Preliminary SN8P1702A/SN8P1703A 8-bit micro-controller build-in 12-bit ADC SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part. Main Office: Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C. Tel: 886-3-551 0520 Fax: 886-3-551 0523 Taipei Office: Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C. Tel: 886-2-2759 1980 Fax: 886-2-2759 8180 Hong Kong Office: Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon. Tel: 852-2723 8086 Fax: 852-2723 9179 Technical Support: Email: Sn8fae@sonix.com.tw MSN: sonix8bit@hotmail.com SONiX TECHNOLOGY CO., LTD Page 112 Revision 0.5 |
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